📄 fwp2-lcd.s
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; Must set AP0-3=2, Writes in User mode cause permission fault
; Reference ARM DDI 0087E, Table 7-3: Interpreting access permission (AP) bits
; Figure 7-6: Small page translation
; Don't complain me that code so complex.
stmfd sp!, {v1-v2}
mrc p15, 0, v1, c2, c0, 0 ; Read Translation Table Base (TTB) register
orr v1, v1, #0xA0000000 ; Translate to Virtual Address
; r0 = Virtual Address, v1 = Translation Base
mov v1, v1, lsr #14
mov v1, v1, lsl #14
mov v2, r0, lsr #(20-2)
bic v2, v2, #0x03
orr v1, v1, v2
ldr v1, [v1] ; v1 = First Level Descriptor
orr v1, v1, #0xA0000000 ; Translate to Virtual Address
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x43
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
mov v1, v1, lsr #10
mov v1, v1, lsl #10
mov v2, r0, lsl #(31-19)
orr v1, v1, v2, lsr #(31-9)
bic v1, v1, #0x03
ldr v1, [v1] ; v1 = Second Level Descriptor
orr v1, v1, #0xA0000000 ; Translate to Virtual Address
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x4B
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
mov v1, v1, lsr #12
mov v1, v1, lsl #12
mov v2, r0, lsl #(31-11)
orr v1, v1, v2, lsr #(31-11)
ldr v2, [v1]
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x4C
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
str v1, [r1], #4
str v2, [r1], #4 ; Save Exception Handler Address
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x4D
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
str r1, [v1] ; Set Exception Handler to SDRAM
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x4E
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
ldmfd sp!, {v1-v2}
; Set Parameter for write to SDRAM Controller
add r0, pc, #WaitSyncFlashReadyBegin-(.+8)
add r2, pc, #WaitSyncFlashReadyDone-(.+8)
WaitSyncFlashReadyMove
cmp r0, r2
beq WaitSyncFlashReadyDone
ldr r3, [r0], #4
str r3, [r1], #4
bal WaitSyncFlashReadyMove
LTORG
WaitSyncFlashReadyBegin
stmfd sp!, {r0, r1, lr} ; save r0, r1
;; Test Only -------------------------------------------
IF SLEEP_DEBUG_MSG
stmfd sp!, {v4-v5}
ldr v4, =UART2_VirtualBase
TestMsgOutput v4, v5, 0x47
ldmfd sp!, {v4-v5}
ENDIF
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
mov r0, #0xA8000000
ldr r1, [r0, #0x04]
ldr r0, [r0, #0x08]
str r0, [sp, #0x08] ; save r0 as return value
str r0, [r1] ; restore IRQ Handler address
; bl FlushDCache
mov r0, #0xA8000000
ldr r0, [r0, #0x00]
bic r0, r0, #0x1F ; Bit 0-4 Should Be Zero
mcr p15, 0, r0, c7, c14, 1 ; Clean and Invalidate DCache entry (using MVA)
;; Test Only -------------------------------------------
IF SLEEP_DEBUG_MSG
stmfd sp!, {v4-v5}
ldr v4, =UART2_VirtualBase
TestMsgOutput v4, v5, 0x48
ldmfd sp!, {v4-v5}
ENDIF
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; Reenable SyncFlash
ldr r0, =SDRAMC_VirtualBase
ldr r1, [r0, #SDCTL1_Offset]
tst r1, #0x80000000
bne WaitSyncFlashReadyDelayDone
; Set Normal Mode
ldr r1, =0x81020300
str r1, [r0, #SDCTL1_Offset]
;; Test Only -------------------------------------------
IF SLEEP_DEBUG_MSG
stmfd sp!, {v4-v5}
ldr v4, =UART2_VirtualBase
TestMsgOutput v4, v5, 0x4A
ldmfd sp!, {v4-v5}
ENDIF
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
ldr r0, =SyncFlash_WakeUpDelayCount
WaitSyncFlashReadyDelay
subs r0, r0, #1
bne WaitSyncFlashReadyDelay
;; Test Only -------------------------------------------
IF SLEEP_DEBUG_MSG
stmfd sp!, {v4-v5}
ldr v4, =UART2_VirtualBase
TestMsgOutput v4, v5, 0x4B
ldmfd sp!, {v4-v5}
ENDIF
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; Set Load Mode Register
ldr r0, =SDRAMC_VirtualBase
ldr r1, =0xB1020300
str r1, [r0, #SDCTL1_Offset]
; Special Read to SyncFlash
ldr r1, =(0xAC000000 :OR: (0x233 :SHL: 10)) ; Burst Length=8, Burst Type=0:Sequential, CAS Latency=3, Operating Mode=0:Standard Operation, Write Burst Mode=1:Single Location Access, Left Shift 10=8(Column A0-A7)+2(A0=A2)
ldr r1, [r1]
; Set Normal Mode
ldr r1, =0x81020300
str r1, [r0, #SDCTL1_Offset]
WaitSyncFlashReadyDelayDone
;; Test Only -------------------------------------------
IF SLEEP_DEBUG_MSG
stmfd sp!, {v4-v5}
ldr v4, =UART2_VirtualBase
TestMsgOutput v4, v5, 0x49
ldmfd sp!, {v4-v5}
ENDIF
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
ldmfd sp!, {r0, r1, pc} ; restore r0, r1, pc
LTORG
WaitSyncFlashReadyDone
; bl FlushDCache
mov r0, #0xA8000000
ldr r0, [r0, #0x00]
bic r0, r0, #0x1F ; Bit 0-4 Should Be Zero
mcr p15, 0, r0, c7, c14, 1 ; Clean and Invalidate DCache entry (using MVA)
DontChangeIRQExceptionHandler
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x44
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
mov r0, #0xA8000000
orr r0, r0, #0x400
mov r1, r0
add lr, pc, #WaitForInterruptBegin-(.+8)
add r2, pc, #WaitForInterruptDone-(.+8)
WaitForInterruptMove
cmp r2, lr
moveq pc, r0
ldr r3, [lr], #4
str r3, [r1], #4
bal WaitForInterruptMove
LTORG
WaitForInterruptBegin
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x51
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; Disable SyncFlash to force to enter power-down mode
ldr r0, =SDRAMC_VirtualBase
ldr r1, =0x01020300
str r1, [r0, #SDCTL1_Offset]
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x52
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; ARM 920T core
; Drain write buffer
nop
mov r2, #0
mcr p15, 0, r2, c7, c10, 4
nop
nop
; Set ARM920T core clock to Fastbus mode
mrc p15, 0, r2, c1, c0, 0
bic r2, r2, #0xC0000000
mcr p15, 0, r2, c1, c0, 0
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x53
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; Entering Stop mode
; Disable MPLL & UPLL
mov r2, #0
ldr r0, =Clock_VirtualBase
ldr r1, [r0, #CSCR_Offset]
bic r1, r1, #0x03
str r1, [r0, #CSCR_Offset]
; Wait for nIRQ/nFIQ
; Wait for interrupt
mcr p15, 0, r2, c7, c0, 4
nop
nop
nop
; Enable MPLL & UPLL
; Done by PLL automatic, just redo and sure it
; ldr r0, =Clock_VirtualBase
; ldr r1, [r0, #CSCR_Offset]
; orr r1, r1, #0x03
; str r1, [r0, #CSCR_Offset]
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x54
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; Set ARM920T core clock to Asynchronous mode
mrc p15, 0, r2, c1, c0, 0
orr r2, r2, #0xC0000000
mcr p15, 0, r2, c1, c0, 0
; Reenable SyncFlash
ldr r0, =SDRAMC_VirtualBase
ldr r1, [r0, #SDCTL1_Offset]
tst r1, #0x80000000
bne WaitForInterruptDelayDone
; Set Normal Mode
ldr r1, =0x81020300
str r1, [r0, #SDCTL1_Offset]
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x55
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
ldr r1, =SyncFlash_WakeUpDelayCount
WaitSyncFlashReadyAgainDelay
subs r1, r1, #1
bne WaitSyncFlashReadyAgainDelay
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x56
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; Set Load Mode Register
ldr r0, =SDRAMC_VirtualBase
ldr r1, =0xB1020300
str r1, [r0, #SDCTL1_Offset]
; Special Read to SyncFlash
ldr r1, =(0xAC000000 :OR: (0x233 :SHL: 10)) ; Burst Length=8, Burst Type=0:Sequential, CAS Latency=3, Operating Mode=0:Standard Operation, Write Burst Mode=1:Single Location Access, Left Shift 10=8(Column A0-A7)+2(A0=A2)
ldr r1, [r1]
; Set Normal Mode
ldr r1, =0x81020300
str r1, [r0, #SDCTL1_Offset]
WaitForInterruptDelayDone
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x57
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
mov pc, lr
LTORG
WaitForInterruptDone
;; Test Only -------------------------------------------
IF SLEEP_DEBUG_MSG
TestMsgOutput v4, v5, 0x46
ldmfd sp!, {v4-v5}
ENDIF
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; bye
ldmfd sp!, {pc}
;---------------------------------------------------------------------------
LEAF_ENTRY DozeWaitForInterrupt
; Entering Doze mode
IF {FALSE}
ldr r0, =GPIO_VirtualBase ; Turn Off LED3(PA23)
ldr r1, [r0, #GPIO_DR_A]
bic r1, r1, #(0x01 :SHL: 23)
str r1, [r0, #GPIO_DR_A]
ENDIF
; Disable MPLL
mov r2, #0
ldr r0, =Clock_VirtualBase
ldr r1, [r0, #CSCR_Offset]
bic r1, r1, #0x01
str r1, [r0, #CSCR_Offset]
; Sleep Here
IF {FALSE}
ldr r0, =GPIO_VirtualBase ; Turn On LED3(PA23)
ldr r1, [r0, #GPIO_DR_A]
orr r1, r1, #(0x01 :SHL: 23)
str r1, [r0, #GPIO_DR_A]
ENDIF
mov pc, lr
;---------------------------------------------------------------------------
LEAF_ENTRY EnableIRQ
;
sub sp, sp, #4
str r1, [sp]
MRS r1, CPSR
BIC r1, r1, #0x80
MSR CPSR_c, r1
ldr r1, [sp]
add sp, sp, #4
;
mov pc, lr
;---------------------------------------------------------------------------
LEAF_ENTRY DisableIRQ
;
sub sp, sp, #4
str r1, [sp]
MRS r1, CPSR
ORR r1, r1, #0x80
MSR CPSR_c, r1
ldr r1, [sp]
add sp, sp, #4
;
mov pc, lr
;---------------------------------------------------------------------------
LEAF_ENTRY EnableFIQ
;
sub sp, sp, #4
str r1, [sp]
MRS r1, CPSR
BIC r1, r1, #0x40
MSR CPSR_c, r1
ldr r1, [sp]
add sp, sp, #4
;
mov pc, lr
;---------------------------------------------------------------------------
LEAF_ENTRY DisableFIQ
;
sub sp, sp, #4
str r1, [sp]
MRS r1, CPSR
ORR r1, r1, #0x40
MSR CPSR_c, r1
ldr r1, [sp]
add sp, sp, #4
;
mov pc, lr
OEMPowerOffEntryString
dcb "OEMPowerOff+", 0x0D, 0x0A, 0x00
OEMPowerOffExitString
dcb "OEMPowerOff-", 0x0D, 0x0A, 0x00
END
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