📄 fwp2-lcd.s
字号:
str r1, [r0, #UART_UFCR]
ldr r1, =0x0047
str r1, [r0, #UART_UBIR]
ldr r1, =0x0270
str r1, [r0, #UART_UBMR]
ldr r1, =0x4021
str r1, [r0, #UART_UCR2]
ldr r1, =0x0000
str r1, [r0, #UART_UCR3]
ldr r1, =0x0040
str r1, [r0, #UART_UCR4]
ldr r1, =0x4027
str r1, [r0, #UART_UCR2]
;-------------------------------------------------------------
; Who am I ?
;-------------------------------------------------------------
; ldr r0, =CopyRightString
; bic r0, r0, #0x80000000
; ldr lr, =Initial_LCDC
; bic lr, lr, #0x80000003
add r0, pc, #CopyRightString-(.+8)
add lr, pc, #Initial_LCDC-(.+8)
bal UART_PutString
LTORG
CopyRightString
dcb 0x0D, 0x0A
; dcb "Motorola, Inc.", 0x0D, 0x0A
dcb "Copyright 2002 Motorola, Inc. All Rights Reserved.", 0x0D, 0x0A
dcb "Motorola DragonBall-MX1 "
IF Platform_MX9328MXLite
dcb "Lite (Corsica) "
ENDIF
dcb "WinCE .NET", 0x0D, 0x0A, 0x00
;-------------------------------------------------------------
; Initialize LCD Controller.
;-------------------------------------------------------------
ALIGN 4
Initial_LCDC
ldr r0, =LCDC_Base
ldr r1, =FRAMEBUFFER_ADDRESS
str r1, [r0, #LCDC_SSA] ; Assign Frame Buffer Address
ldr r1, =0x014000F1 ;0x014000F0,0x01400140(for sharp)
;;; ldr r1, =0x014000F0
str r1, [r0, #LCDC_SIZE] ; Size Register
ldr r1, =0x000000A0 ; 78
str r1, [r0, #LCDC_VPW] ; Virtual Page Width
; Cursor
ldr r1, =0x40010001
str r1, [r0, #LCDC_CPOS]
ldr r1, =0x1F1F0000
str r1, [r0, #LCDC_LCWHB]
ldr r1, =0x0000F800
str r1, [r0, #LCDC_LCHCC]
; Cursor OFF
ldr r1, =0x00000000
str r1, [r0, #LCDC_CPOS]
; Panel Configuration Register
IF !MX1LLCD_REVC
ldr r1, =0xF8008B42 ;0xF8C88083(FOR taiwan) Set to Little Endian;0xF8008B42(FOR SHARP)
ELSE
ldr r1, =0xF9C88083 ; Set to Little Endian, Pixel Polarity high for LCD RevC
ENDIF
str r1, [r0, #LCDC_PCR]
ldr r1, =0x04000F06 ;0x04000405(for taiwan),0x04000F06(for sharp)0x24002025 0x2000101E(for samsung)
str r1, [r0, #LCDC_HCR] ; hsyn width = 12 hsyn_wait 1 = 15 hsyn_wait2 = 15 (for sharp)
;;; ldr r1, =0x04000907
;;ldr r1, =0x04000B03
ldr r1, =0x04000B07 ; 0x08000100(for taiwan) 0x04000B07(for sharp)0x1000020D 0x20000407(for samsung)
str r1, [r0, #LCDC_VCR] ; vsyn width = 1 vsyn_wait 1 = 0 vsyn_wait2 = 4 (for sharp)
ldr r1, =0x00000000
str r1, [r0, #LCDC_RMCR] ; Size Register
;ldr r1, =0x00080008
ldr r1, =0x00040008
str r1, [r0, #LCDC_DMACR] ; DMA Control Register
ldr r1, =0x0C090073
ldr r1, =0x00090373
str r1, [r0, #LCDC_LGPMR]
; Enable LCDC
;;; ldr r1, =0x00008200
ldr r1, =0x00A98200
str r1, [r0, #LCDC_PWMR]
ldr r1, =0x0F000002
str r1, [r0, #LCDC_RMCR]
IF !MX1LLCD_REVC
;;; ldr r1, =0x00000200
ldr r1, =0x00A90200
ELSE
ldr r1, =0x00A9038A ;; For LCD Rev C, use bits CC_EN and PW for backlight
ENDIF
str r1, [r0, #LCDC_PWMR]
; Delay
mov r0, #0x600
35
subs r0, r0, #1
bne %b35
IF !Platform_MX9328MXLite
ldr r0, =GPIO_Base ; Turn On LCD backlight
ldr r1, [r0, #GPIO_DR_C]
orr r1, r1, #0x00010000 ;0x00010000
str r1, [r0, #GPIO_DR_C]
ENDIF
;; ADD BY HLJ
IF Platform_MX9328MXLite
ldr r0, =GPIO_Base ; Turn On LCD backlight
ldr r1, [r0, #GPIO_DR_D]
orr r1, r1, #0x00000800 ;0x00010000
str r1, [r0, #GPIO_DR_D]
ENDIF
;; ADD BY HLJ
;-------------------------------------------------------------
; Ready to start Kernel and Enter KernelStart...
;-------------------------------------------------------------
;;; mov r0, #0x00300000 ; Set SP to internal SRAM
;;; ldr r0, =0x12300000 ; Set SP to external SRAM
ldr r0, =0x0B000000 ; Set SP to external SDRAM
add sp, r0, #0x20000 ; temp stack for initialization (128KB)
ldr r0, =FRAMEBUFFER_ADDRESS ; (r0) = ptr to display buffer
IF {FALSE}
IF :LNOT: IMAGE_IN_ROM
ldr r1, =0xF800F800 ; RED color in RGB565 TFT LCD
add r2, r0, #0x9600 ; clear out 320x240x2
10 str r1, [r0], #4
cmp r0, r2
blo %B10
ldr r1, =0x07C007C0 ; GREEN color in RGB565 TFT LCD
add r2, r0, #0x9600 ; clear out 320x240x2
20 str r1, [r0], #4
cmp r0, r2
blo %B20
ldr r1, =0x001F001F ; BLUE color in RGB565 TFT LCD
add r2, r0, #0x9600 ; clear out 320x240x2
30 str r1, [r0], #4
cmp r0, r2
blo %B30
ELSE ;:LNOT: IMAGE_IN_ROM
bal ShowTechwareLogo ; Show up Techware Logo
LTORG
TechwareLogo
OPT 2 ; disable listing
;INCBIN LOGO.BIN ;; Poor WinCE ARM Assembler, don't support INCBIN directives
INCLUDE Logo.s
OPT 1 ; reenable listing
ShowTechwareLogo
; Fill with White color
mvn a2, #0
ldr a3, =(320*240*2)
mov a4, a1
10
str a2, [a4], #4
subs a3, a3, #4
bne %b10
add a1, a1, #(240*2*80)
ldr a2, =TechwareLogo
bic a2, a2, #0x80000000
ldr a3, =(ShowTechwareLogo - TechwareLogo)
20
ldr a4, [a2], #4
;;;mov a4, a4, ror #16 ; for Big Endian
str a4, [a1], #4
subs a3, a3, #4
bne %b20
ENDIF ;:LNOT: IMAGE_IN_ROM
ELSE
; Fill with Blue color like as Windows Style (Blue Screen)
mov a2, #0x001F
orr a2, a2, a2, lsl #16
ldr a3, =(320*240*2)
mov a4, a1
10
str a2, [a4], #4
subs a3, a3, #4
bne %b10
ENDIF
;-------------------------------------------------------------
;-------------------------------------------------------------
BL FlushDCache
;-------------------------------------------------------------
; Pass the OEMAddressTable address and enter to KernelStart
; (r0) = physical address of OEMAddressTable
;-------------------------------------------------------------
add r0, pc, #OEMAddressTable-(.+8)
bl KernelStart
;-------------------------------------------------------------
; KernelStart should never return:
;-------------------------------------------------------------
spin
; LED display DEAD...
b spin
;---------------------------------------------------------------------------
; For User Diagnostic functions.
;---------------------------------------------------------------------------
LEAF_ENTRY ReadCPCon1
; Read control register 1 of CP15.
MRC p15, 0, r0, c1, c0, 0
mov pc, lr
LEAF_ENTRY DisableCache
; Disable Instruction and Data cache.
MRC p15, 0, r0, c1, c0, 0
BIC r0, r0, #(1<<2) ; 0x4
BIC r0, r0, #(1<<12) ; 0x1000
MCR p15, 0, r0, c1, c0, 0
mov pc, lr
LEAF_ENTRY DummyFunc
; Just return..
NOP
mov pc, lr
;---------------------------------------------------------------
; Set Clock as Asynchronous Mode
;---------------------------------------------------------------
LEAF_ENTRY SetAsyncMode
; To set the iA bit and the nF bit of CP15 register 1.
mrc p15, 0, r0, c1, c0, 0
mov r2, #0xC0000000
orr r0, r2, r0
mcr p15, 0, r0, c1, c0, 0
;
mov pc, lr
;---------------------------------------------------------------------------
;---------------------------------------------------------------------------
UART_PutString
IF DEBUG_PORT_COM2
ldr r1, =UART2_Base
ELSE
ldr r1, =UART1_Base
ENDIF
34
ldr r2, [r1, #UART_UTS]
tst r2, #0x10
bne %b34
ldrb r2, [r0], #1
movs r2, r2
strne r2, [r1, #UART_UTXD]
bne %b34
mov pc, lr
;---------------------------------------------------------------------------
; Memory configuration should be optimized for best performance
; The following parameter is not optimized.
; Memory access cycle parameter strategy
;---------------------------------------------------------------------------
LTORG
;---------------------------------------------------------------------------
; Include the appropriate memory map.
INCLUDE map920.h
TECHWARE DATA
dcd 0x54, 0x45, 0x43, 0x48, 0x57, 0x41, 0x52, 0x45, 0x00
;---------------------------------------------------------------------------
; Power Management. Suspend and WakeUp
;---------------------------------------------------------------------------
GBLL SLEEP_DEBUG_MSG
SLEEP_DEBUG_MSG SETL {FALSE}
; Store Data Table
; 0x08000000: 0xFFFF03F8=>IRQ Exception Handler Address
; 0x08000004: =>The pointer point to Physical Address of IRQ Exception Handler Address + 0xA0000000
; 0x08000008: =>The value of IRQ Exception Handler Address
MACRO
TestMsgOutput $Base, $Tmp, $Val
IF SLEEP_DEBUG_MSG
mov $Tmp, #$Val
str $Tmp, [$Base, #UART_UTXD]
921
ldr $Tmp, [$Base, #UART_USR2]
tst $Tmp, #0x08
beq %b921
ENDIF
MEND
TEXTAREA
ldr r0, =OEMPowerOffEntryString
bal UART_PutString
mov pc, lr
LEAF_ENTRY SleepWaitForInterrupt
stmfd sp!, {lr}
;; Test Only -------------------------------------------
IF SLEEP_DEBUG_MSG
stmfd sp!, {v4-v5}
ldr v4, =UART2_VirtualBase
TestMsgOutput v4, v5, 0x50
TestMsgOutput v4, v5, 0x61
TestMsgOutput v4, v5, 0x75
TestMsgOutput v4, v5, 0x6C
TestMsgOutput v4, v5, 0x2C
TestMsgOutput v4, v5, 0x20
TestMsgOutput v4, v5, 0x43
TestMsgOutput v4, v5, 0x68
TestMsgOutput v4, v5, 0x61
TestMsgOutput v4, v5, 0x6F
TestMsgOutput v4, v5, 0x0D
TestMsgOutput v4, v5, 0x0A
ENDIF
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; Failure to wakeup the system from STOP mode, if the vector table stored at SyncFlash.
; Fix status: The Metal-fix on the next mask release 1L45N.
; Dirty Code to Do SyncFlash Wakeup Delay
mrc p15, 0, r0, c1, c0, 0
tst r0, #(0x01 :SHL: 13) ; V bit: Base location of exception registers
ldreq r0, =0x00000000 ; 0 = Low addresses = 0x00000000
ldrne r0, =0xFFFF0000 ; 1 = High addresses = 0xFFFF0000
add r0, r0, #0x18 ; IRQ Exception Handler address
stmfd sp!, {r0}
ldr r0, [r0] ; Maybe 0xE59FF3D8
ldr r1, =0xE59FF000 ; binary code for instruction "ldr pc, [pc, #0x???]
mvn r2, #0 ; r2 = 0xFFFFFFFF
mov r2, r2, lsl #12 ; r2 = 0xFFFFF000
and r3, r0, r2
cmp r1, r3
ldmnefd sp!, {r0}
bne DontChangeIRQExceptionHandler
mvn r2, r2
and r3, r0, r2
ldmfd sp!, {r0}
add r0, r0, #8
add r0, r3, r0 ; r0 = The address that store the IRQ Exception Handler
mov r1, #0xA8000000
str r0, [r1], #4 ; save IRQ Exception Handler Address
;; Test Only -------------------------------------------
TestMsgOutput v4, v5, 0x42
;; Test Only +++++++++++++++++++++++++++++++++++++++++++
; Because the Exception Handler Table(0xFFFFxxxx) is AP0-3=0, S=0, R=1, Any write generates a permission fault
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -