📄 fwp2-lcd.s
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;---------------------------------------------------------------------------
; TITLE("MC9328MX1 Firmware Initialization")
;++
;
; Copyright 2002 Motorola, Inc. All Rights Reserved.
;
; Module Name:
;
; fwp2.s
;
; Abstract:
;
; This module implements the code necessary to initialize the HW and
; Kernel interface routines.
;
;---------------------------------------------------------------------------
; Modified full codes for MC9328MX1...
;---------------------------------------------------------------------------
OPT 2 ; disable listing
INCLUDE kxarm.h
INCLUDE oalintra.inc
OPT 1 ; reenable listing
OPT 128 ; disable listing of macro expansions
;---------------------------------------------------------------------------
; Define special register physical location
;---------------------------------------------------------------------------
include MC9328MX1.inc
;---------------------------------------------------------------------------
;---------------------------------------------------------------------------
IMPORT KernelStart
IMPORT OEMInitDebugSerial
IMPORT TLBClear
IMPORT FlushICache
IMPORT FlushDCache
IF MX1LADS_VER20
FlashPABase EQU 0x10000000
ELSE
FlashPABase EQU 0x0C000000
ENDIF
EbootImageSize EQU 0x00020000
STARTUPTEXT
LEAF_ENTRY StartUp
;-------------------------------------------------------------
; Initialize Clock, PLL and Memory control Registers...
;-------------------------------------------------------------
; Save the Ethernet MAC address
IF :LNOT: MX1LADS_VER20
;;;;; No longer used for Release 2.1.0 onwards for both ADS 1.x and ADS 2.0
;;;;; The MAC address can be modified in the file 'Cs8900a.c' under
;;;;; $(_TARGETPLATROOT)\drivers\ETHDBG\cs8900a directory
;bal ActualyStart
;DCB 0x12, 0x13, 0x17, 0x28, 0x30, 0x02 ; MAC=12.13.17.28.31.00
;DCB 0x00, 0x00 ; Dummy byte for align dword
ENDIF ; IF :LNOT: MX1LADS_VER20
ActualyStart
; Turn Off MMU
IF :LNOT: BOOTLOADER
ldr lr, =ActualyFlashAddress
ELSE
; get pc relative address
adr lr, ActualyFlashAddress
ENDIF
bic lr, lr, #0x80000003
mov r0, #0x78
mcr p15, 0, r0, c1, c0, 0
mov pc, lr
ActualyFlashAddress
nop
nop
; Change to Supervisor mode
mov r0, #(SVCmode:OR:IRQDisable:OR:FIQDisable) ; No interrupts
msr cpsr_c, r0
; Clear TLB & Flush Cache area.
bl TLBClear
bl FlushICache
nop
nop
nop
;-------------------------------------------------------------
; Disable all Interrupts
;-------------------------------------------------------------
ldr r0, =Int_Base
mov r1, #0
str r1, [r0, #INTCNTL_Offset] ; Config Interrupt service
str r1, [r0, #INTENABLEH_Offset] ; Interrupt service is Disabled
str r1, [r0, #INTENABLEL_Offset] ; Interrupt service is Disabled
;-------------------------------------------------------------
; Set up PLL Clock & System Control
;-------------------------------------------------------------
ldr sp, =(Int_Base+NIPRIORITY0_Offset) ; Put Stack pointer in AITC Priority Register
IMPORT PMU_Init
IMPORT SystemControl_Init
bl PMU_Init ; Init PMU for system
bl SystemControl_Init
;-------------------------------------------------------------
; Make AsyncBusMode...
;-------------------------------------------------------------
bl SetAsyncMode
;-------------------------------------------------------------
; Dummy for delay time
;-------------------------------------------------------------
mov r0, #0x2000
5 subs r0, r0, #1
bne %B5
;-------------------------------------------------------------
;Set SDRAM control registers for CSD0 - CSD1
;-------------------------------------------------------------
IF IMAGE_IN_ROM
ldr r0, =SDRAMC_Base
IF :LNOT: BOOTLOADER
mov r1, pc
ldr r2, =(FlashPABase+EbootImageSize)
cmp r1, r2
bgt SdramInitDone ; skip sdram init if os image with eboot offset
ENDIF
IF MX1LADS_VER20
ldr r1, =0x92120200
ldr r2, =0x08200000
str r1, [r0, #SDCTL0_Offset] ; Set Precharge Command
str r1, [r2, #0] ; Issue Precharge all Command
ldr r1, =0xA2120200
ldr r2, =0x08000000
str r1, [r0, #SDCTL0_Offset] ; Set AutoRefresh Command
str r1, [r2, #0] ; Issue AutoRefresh Command
str r1, [r2, #0]
str r1, [r2, #0]
str r1, [r2, #0]
str r1, [r2, #0]
str r1, [r2, #0]
str r1, [r2, #0]
str r1, [r2, #0]
ldr r1, =0xB2120200
ldr r2, =0x08111800
str r1, [r0, #SDCTL0_Offset] ; Set Mode Register
str r1, [r2, #0] ; Issue Mode Register Command
; Burst Length = 8
ldr r1, =0x8212C267
str r1, [r0, #SDCTL0_Offset] ; Set to Normal Mode
ELSE ; IF MX1LADS_VER20
ldr r1, =0x92120200
str r1, [r0, #SDCTL0_Offset] ; Set Precharge Command
ldr r1, =0x08200000
ldr r1, [r1] ; Issue Precharge all Command
ldr r1, =0xA2120200
str r1, [r0, #SDCTL0_Offset] ; Set AutoRefresh Command
ldr r1, =0x08000000 ; Issue AutoRefresh Command
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r2, [r1]
ldr r1, =0xB2120200
str r1, [r0, #SDCTL0_Offset] ; Set Mode Register
ldr r1, =0x08111800 ; Issue Mode Register Command
ldr r1, [r1] ; Burst Length = 8
ldr r1, =0x8212C267
str r1, [r0, #SDCTL0_Offset] ; Set to Normal Mode
ENDIF ; IF MX1LADS_VER20
SdramInitDone
ENDIF
; If Image isn't in SyncFlash, Initialize SyncFlash
IF IMAGE_IN_ROM
IF MX1LADS_VER20
ldr r1, =0x81020300
str r1, [r0, #SDCTL1_Offset]
b SyncFlashSetupDone
ELSE ; IF MX1LADS_VER20
and r1, pc, #0x1F000000
cmp r1, #0x0C000000
ldrne r1, =0x81020300
strne r1, [r0, #SDCTL1_Offset]
bne SyncFlashSetupDone
ENDIF ; IF MX1LADS_VER20
; Set Parameter for write to SDRAM Controller
mov r1, #0x08000000
add lr, pc, #SyncFlashSetupBegin-(.+8)
add r2, pc, #SyncFlashSetupDone-(.+8)
SyncFlashSetupMove
cmp r2, lr
moveq pc, #0x08000000
ldr r3, [lr], #4
str r3, [r1], #4
bal SyncFlashSetupMove
LTORG
SyncFlashSetupBegin
; Set Normal Mode
ldr r1, =0x81020300
str r1, [r0, #SDCTL1_Offset]
IF {TRUE}
; Set Pre-Charge Mode
ldr r1, =0x91020300
str r1, [r0, #SDCTL1_Offset]
; Special Read to SyncFlash
ldr r1, =0x0C100000
ldr r1, [r1]
ENDIF
; Set Load Mode Register
ldr r1, =0xB1020300
str r1, [r0, #SDCTL1_Offset]
; Special Read to SyncFlash
ldr r1, =(0x0C000000 :OR: (0x233 :SHL: 10)) ; Burst Length=8, Burst Type=0:Sequential, CAS Latency=3, Operating Mode=0:Standard Operation, Write Burst Mode=1:Single Location Access, Left Shift 10=8(Column A0-A7)+2(A0=A2)
; ldr r1, =0x0C08CC00
ldr r1, [r1]
IF {FALSE}
; Set Pre-Charge Mode
ldr r1, =0x91020300
str r1, [r0, #SDCTL1_Offset]
; Special Read to SyncFlash
ldr r1, =0x0C100000
ldr r1, [r1]
ENDIF
; Set Normal Mode
ldr r1, =0x81020300
str r1, [r0, #SDCTL1_Offset]
mov pc, lr
LTORG
SyncFlashSetupDone
ENDIF
; Set Stack Pointer
mov sp, #(0x08000000 + (1024 * 1024))
sub sp, sp, #4
;-------------------------------------------------------------
;Set EIM control registers for CS0 - CS5
;-------------------------------------------------------------
ldr r0, =EIM_Base
IF MX1LADS_VER20
;Config CS0 for NOR Flash
ldr r1, =0x00000801
str r1, [r0, #EIM_CS0U]
ldr r1, =0x11110E01
str r1, [r0, #EIM_CS0L]
ELSE
; for ADS v1.0 Rev.B
; Config CS0 ; DOC SODIMM setting
;ldr r1, =0x0000B070
;str r1, [r0, #EIM_CS0U]
;ldr r1, =0xFFFFF501
;str r1, [r0, #EIM_CS0L]
ENDIF
IF MX1LADS_VER20
; Config CS1 ; SRAM SODIMM setting
ldr r1, =0x00000A00 ; Set 10 Wait state for SRAM
str r1, [r0, #0x08]
ldr r1, =0x11110601
str r1, [r0, #0x0C]
ELSE ; IF MX1LADS_VER20
; for ADS v1.0 Rev.B
; Config CS1 ; DOC SODIMM setting
ldr r1, =0x0000B070
str r1, [r0, #EIM_CS1U]
ldr r1, =0xFFFFF501
str r1, [r0, #EIM_CS1L]
ENDIF ;IF MX1LADS_VER20
; Config CS4 ; UART SODIMM/CS8900 Ethernet setting
ldr r1, =0x00000F00
str r1, [r0, #EIM_CS4U]
ldr r1, =0x00001501
str r1, [r0, #EIM_CS4L]
; Config CS5 ; PD6710 (PCMCIA) SODIMM setting
ldr r1, =0x0000FF70 ;
str r1, [r0, #EIM_CS5U]
ldr r1, =0x0000F501
str r1, [r0, #EIM_CS5L]
;-------------------------------------------------------------
; Disable all Interrupts
;-------------------------------------------------------------
ldr r0, =Int_Base
mov r1, #0
str r1, [r0, #INTCNTL_Offset] ; Config Interrupt service
str r1, [r0, #INTENABLEH_Offset] ; Interrupt service is Disabled
str r1, [r0, #INTENABLEL_Offset] ; Interrupt service is Disabled
str r1, [r0, #INTTYPEH_Offset] ; IRQ mode
str r1, [r0, #INTTYPEL_Offset] ; IRQ mode
str r1, [r0, #INTFRCH_Offset] ; Clear Interrupt Force Register
str r1, [r0, #INTFRCL_Offset] ; Clear Interrupt Force Register
ldr r1, =0x44444444 ; Set Default Priority = 4
str r1, [r0, #NIPRIORITY0_Offset]
str r1, [r0, #NIPRIORITY1_Offset]
str r1, [r0, #NIPRIORITY2_Offset]
str r1, [r0, #NIPRIORITY3_Offset]
str r1, [r0, #NIPRIORITY4_Offset]
str r1, [r0, #NIPRIORITY5_Offset]
str r1, [r0, #NIPRIORITY6_Offset]
str r1, [r0, #NIPRIORITY7_Offset]
ldr r1, [r0, #NIPRIORITY0_Offset]
bic r1, r1, #(0x0F :SHL: ((5 :MOD: 8) * 4)) ; Clear PenUp priority
orr r1, r1, #(0x0D :SHL: ((5 :MOD: 8) * 4)) ; Set PenUp as First priority
str r1, [r0, #NIPRIORITY0_Offset] ; Clear Interrupt Priority
ldr r1, [r0, #NIPRIORITY4_Offset]
bic r1, r1, #(0x0F :SHL: ((33 :MOD: 8) * 4)) ; Clear PenSample priority
orr r1, r1, #(0x0C :SHL: ((33 :MOD: 8) * 4)) ; Set PenSample as Second priority
str r1, [r0, #NIPRIORITY4_Offset] ; Clear Interrupt Priority
ldr r1, [r0, #NIPRIORITY5_Offset]
bic r1, r1, #(0x0F :SHL: ((46 :MOD: 8) * 4)) ; Clear PenDown priority
orr r1, r1, #(0x0B :SHL: ((46 :MOD: 8) * 4)) ; Set PenDown as Second priority
str r1, [r0, #NIPRIORITY5_Offset] ; Clear Interrupt Priority
ldr r1, [r0, #NIPRIORITY7_Offset]
bic r1, r1, #(0x0F :SHL: ((59 :MOD: 8) * 4)) ; Clear Timer1 (Reschedule Timer) priority
orr r1, r1, #(0x0F :SHL: ((59 :MOD: 8) * 4)) ; Set Timer1 (Reschedule Timer) as first priority
bic r1, r1, #(0x0F :SHL: ((61 :MOD: 8) * 4)) ; Clear DMA priority
; GSG-SGP <29-JUL-03> <WINCE_13> : Change DMA to first priority
orr r1, r1, #(0x0F :SHL: ((61 :MOD: 8) * 4)) ; Set DMA as First priority
str r1, [r0, #NIPRIORITY7_Offset] ; Clear Interrupt Priority
mvn r1, #0
str r1, [r0, #NIMASK_Offset] ; Config Interrupt Mask to accept all priority interrupt
;-------------------------------------------------------------
; Initialize GPIO Ports
;-------------------------------------------------------------
IMPORT GPIO_Init_ROM
bl GPIO_Init_ROM
;-------------------------------------------------------------
; Initialize UART in 115200 N-8-1, No flow. for Debugger.
;-------------------------------------------------------------
IF DEBUG_PORT_COM2
ldr r0, =UART2_Base
ELSE
ldr r0, =UART1_Base
ENDIF
mov r1, #0
str r1, [r0, #UART_UCR2] ; Reset UART
33
ldr r1, [r0, #UART_UTS] ; Clear Receive Buffer
tst r1, #0x20
ldreq r1, [r0, #UART_URXD]
beq %b33
ldr r1, =0x0005
str r1, [r0, #UART_UCR1]
ldr r1, =0x0D8A
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