syslib.c

包含makefile config.h rominit romstart userinit 等等文件

/* sysLib.c - ARM Integrator system-dependent routines */

/* Copyright 1999-2001 ARM Limited */
/* Copyright 1999-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"

/*
modification history
--------------------
2004/10/23 this file is modified form VxWorks demo bsp integrator920t

*/

/*
DESCRIPTION
This library provides board-specific routines for the ARM Integrator
Development Board BSP.

It #includes the following chip drivers:
    nullVme.c -         dummy VMEbus routines
    ambaTimer.c -       AMBA timer driver
    ambaIntrCtl.c -     AMBA interrupt controller driver
    primeCellSio.c -	PrimeCell UART driver
    pciIomapLib.c -	PCI I/O mapping support
if INCLUDE_FLASH is defined, it #includes:
    flashMem.c -        Flash memory driver
    nvRamToFlash.c -    driver to use some Flash like NVRAM
else it #includes:
    nullNvRam.c -	dummy NVRAM routines

It #includes the following BSP files:
    sysSerial.c -	serial device initialisation routines
    sysEnd.c -		END network driver support routines.
    pciIomapShow.c -	PCI Show routines

INCLUDE FILES: sysLib.h string.h intLib.h taskLib.h vxLib.h muxLib.h
	       pciIomapLib.h

SEE ALSO:
.pG "Configuration"
.I "ARM Architecture Reference Manual,"
.I "ARM 7TDMI Data Sheet,"
.I "ARM 720T Data Sheet,"
.I "ARM 740T Data Sheet,"
.I "ARM 920T Technical Reference Manual",
.I "ARM 940T Technical Reference Manual",
.I "ARM 946E-S Technical Reference Manual",
.I "ARM 966E-S Technical Reference Manual",
.I "ARM Reference Peripherals Specification,"
.I "ARM Integrator/AP User Guide",
.I "ARM Integrator/CM7TDMI User Guide",
.I "ARM Integrator/CM720T User Guide",
.I "ARM Integrator/CM740T User Guide",
.I "ARM Integrator/CM920T User Guide",
.I "ARM Integrator/CM940T User Guide",
.I "ARM Integrator/CM946E User Guide",
.I "ARM Integrator/CM9x6ES Datasheet".
*/

/* includes */

#include "vxWorks.h"
#include "config.h"

#include "sysLib.h"
#include "string.h"
#include "intLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "muxLib.h"
#include "cacheLib.h"

#if defined(CPU_920T)
#include "arch/arm/mmuArmLib.h"
#include "private/vmLibP.h"
/*#include "dllLib.h"*/
#endif /* defined(720T/740T/920T/940T/946ES) */


/* imports */

IMPORT char end [];			    /* end of system, created by ld */
IMPORT VOIDFUNCPTR _func_armIntStackSplit;  /* ptr to fn to split stack */



#if !defined(INCLUDE_MMU) && \
    (defined(INCLUDE_CACHE_SUPPORT) || defined(INCLUDE_MMU_BASIC) || \
     defined(INCLUDE_MMU_FULL) || defined(INCLUDE_MMU_MPU))
#define INCLUDE_MMU
#endif


/* globals */

#if defined(INCLUDE_MMU)
#if defined(CPU_920T)

/*
 * The following structure describes the various different parts of the
 * memory map to be used only during initialisation by
 * vm(Base)GlobalMapInit() when INCLUDE_MMU_BASIC/FULL are
 * defined.
 *
 * Clearly, this structure is only needed if the CPU has an MMU!
 *
 * The following are not the smallest areas that could be allocated for a
 * working system. If the amount of memory used by the page tables is
 * critical, they could be reduced.
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
{
    /* adrs and length parameters must be page-aligned (multiples of 0x1000) */


	/* ram header 16K */
	{
		(void *) 0,	/* virtual address */
		(void *) 0,	/* physical address */
		ROUND_UP (ARM920T_SSRAM_SIZE, PAGE_SIZE), /* length, then initial state: */
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE
	},

	/* internal rom 128K*/
    {
		(void *) ARM920T_INT_ROM_BASE,
		(void *) ARM920T_INT_ROM_BASE,
		ROUND_UP (ARM920T_SSRAM_SIZE, PAGE_SIZE),
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE_NOT
	},
		

    /*
     * ROM is normally marked as uncacheable by VxWorks. We leave it like that
     * for the time being, even though this has a severe impact on execution
     * speed from ROM.
     */
    {
    (void *) ROM_BASE_ADRS,
    (void *) ROM_BASE_ADRS,
    ROUND_UP (ROM_SIZE_TOTAL, PAGE_SIZE),
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
#ifdef INCLUDE_FLASH
    /* needs to be writable */

    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
#else
    VM_STATE_VALID	| VM_STATE_WRITABLE_NOT  | VM_STATE_CACHEABLE_NOT
#endif
    },

    /* DRAM */
    {
    (void *) LOCAL_MEM_LOCAL_ADRS,	/* virtual address */
    (void *) LOCAL_MEM_LOCAL_ADRS,	/* physical address */
    ROUND_UP (LOCAL_MEM_SIZE, PAGE_SIZE), /* length, then initial state: */
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE
    },


    /*
     * I/O space:
     * Do not map in all I/O space, only that which has something there.
     * Otherwise we will use all of RAM allocating page tables!
     */
    {
		(void *) AIC_BASE_ADDR,	/* Core Module Header regs */
		(void *) AIC_BASE_ADDR,
		ROUND_UP (0x4000,PAGE_SIZE),
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
    },

    {
		(void *) TIMER0_BASE_ADDR,	
		(void *) TIMER0_BASE_ADDR,
		ROUND_UP (2*0x4000,PAGE_SIZE),
		VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
		VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
	},
	
#ifdef	INCLUDE_USB
		{
			(void *) USB_DEV_BASE_ADDR,	
			(void *) USB_DEV_BASE_ADDR,
			ROUND_UP (0x4000,PAGE_SIZE),
			VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
			VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
		},
#endif


#ifdef	INCLUDE_AT91_MULT_CARD
		{
			(void *) MULT_CARD_BASE_ADDR,	
			(void *) MULT_CARD_BASE_ADDR,
			ROUND_UP (0x4000,PAGE_SIZE),
			VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
			VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
		},
#endif

#ifdef	INCLUDE_AT91_TWO_WIRE_IF
		{
			(void *) TWO_WIRE_IF_BASE_ADDR,	
			(void *) TWO_WIRE_IF_BASE_ADDR,
			ROUND_UP (0x4000,PAGE_SIZE),
			VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
			VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
		},
#endif

#ifdef	INCLUDE_AT91EMAC_END
		{
			(void *) ETH_MAC_BASE_ADDR,	
			(void *) ETH_MAC_BASE_ADDR,
			ROUND_UP (0x4000,PAGE_SIZE),
			VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
			VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
		},
#endif

#ifdef	INCLUDE_SERIAL
		{
			(void *) UART0_BASE_ADDR,	
			(void *) UART0_BASE_ADDR,
			ROUND_UP (4*0x4000,PAGE_SIZE),
			VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
			VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
		},
#endif
			
#ifdef	INCLUDE_AT91_SYNC_SERIAL
		{
			(void *) SER_SYNC_CONTROL_BASE_ADDR,	
			(void *) SER_SYNC_CONTROL_BASE_ADDR,
			ROUND_UP (3*0x4000,PAGE_SIZE),
			VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
			VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
		},
#endif
			
#ifdef	INCLUDE_AT91_SPI
		{
			(void *) SPI_DEV_BASE_ADDR,	
			(void *) SPI_DEV_BASE_ADDR,
			ROUND_UP (0x4000,PAGE_SIZE),
			VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
			VM_STATE_VALID	| VM_STATE_WRITABLE	 | VM_STATE_CACHEABLE_NOT
		},
#endif
			
			
};

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);
#endif /* defined(CPU_920T)*/

#endif /* defined(INCLUDE_MMU) */

int	sysBus	    = BUS;		/* system bus type (VME_BUS, etc) */
int	sysCpu	    = CPU;		/* system CPU type (e.g. ARMARCH4/4_T)*/
char *	sysBootLine = BOOT_LINE_ADRS; 	/* address of boot line */
char *	sysExcMsg   = EXC_MSG_ADRS;	/* catastrophic message area */
int	sysProcNum;			/* processor number of this CPU */
int	sysFlags;			/* boot flags */
char	sysBootHost [BOOT_FIELD_LEN];	/* name of host from which we booted */
char	sysBootFile [BOOT_FIELD_LEN];	/* name of file from which we booted */


/* locals */


/* defines */


/* externals */
IMPORT void   At91IntDevInit (void);
IMPORT void sysIntStackSplit (char *, long);


/* globals */


/* forward LOCAL functions declarations */


/* forward declarations */

char *	sysPhysMemTop (void);


#if defined (INCLUDE_USB)
void sysUsbPciInit(void);
#endif

/* included source files */

#ifdef INCLUDE_FLASH
#include "mem/nvRamToFlash.c"
#include "flashMem.c"
#else
#include "mem/nullNvRam.c"
#endif
#include "vme/nullVme.c"

#include "at91dbgu.c"
#include "at91intrctl.c"
#include "at91pdc.c"
#include "at91pio.c"
#include "at91pmc.c"
#include "at91sysTimer.c"
#include "at91uart.c"
#include "at91vxwtimer.c"
#include "sysSerial.c"






/*
 *	before start up, we disable all devices interrupt, stop all PDC
 */

void Disable_All_Device()
{
	/*
	 *	we disable device accrod PID
	 */
	UINT32 tmp = 0xFFFFFFFF;
	UINT32 dummy;

	/*
	 *	AIC
	 */
	( (AIC_S*)AIC_BASE_ADDR ) ->AIC_IDCR = tmp;
	dummy = ( (AIC_S*)AIC_BASE_ADDR ) ->AIC_IVR;
	dummy = ( (AIC_S*)AIC_BASE_ADDR ) ->AIC_FVR;

	/*
	 *	SYS timer, DBGU, PMC..
	 */
	( (SYSTIMER_S*)SYSTIMER_BASE_ADDR ) ->ST_IDR = tmp;
	( (DBGU_S*)DBGU_BASE_ADDR ) ->DBGU_IDR = tmp;
	( (PMC_S*)PMC_BASE_ADDR ) ->PMC_IDR = tmp;
	( (RTC_S*)RTC_BASE_ADDR ) ->RTC_IDR = tmp;
	


	/*
	 *	PIO
	 */
	( (AT91_PIO_S*)PIOA_BASE_ADDR ) ->PIO_IDR = tmp;
	( (AT91_PIO_S*)PIOB_BASE_ADDR ) ->PIO_IDR = tmp;
	( (AT91_PIO_S*)PIOC_BASE_ADDR ) ->PIO_IDR = tmp;
	( (AT91_PIO_S*)PIOD_BASE_ADDR ) ->PIO_IDR = tmp;
	
	/*
	 *	UART 
	 */
	( (UART_S*)UART0_BASE_ADDR ) ->US_IDR = tmp;
	( (UART_S*)UART1_BASE_ADDR ) ->US_IDR = tmp;
	( (UART_S*)UART2_BASE_ADDR ) ->US_IDR = tmp;
	( (UART_S*)UART3_BASE_ADDR ) ->US_IDR = tmp;
	AT91_PDC_Close( &( ( (UART_S*)UART0_BASE_ADDR ) ->US_PDC ) );
	AT91_PDC_Close( &( ( (UART_S*)UART1_BASE_ADDR ) ->US_PDC ) );
	AT91_PDC_Close( &( ( (UART_S*)UART2_BASE_ADDR ) ->US_PDC ) );
	AT91_PDC_Close( &( ( (UART_S*)UART3_BASE_ADDR ) ->US_PDC ) );
		
		
	/*
	 *	MCI
	 */

	( (MCI_S*)MCI_BASE_ADDR ) ->MCI_IDR = tmp;
	AT91_PDC_Close( &( ( (MCI_S*)MCI_BASE_ADDR ) ->MCI_PDC ) );

	/*
	 *	UDP
	 */
	( (UDP_S*)UDP_BASE_ADDR ) ->UDP_IDR = tmp;

	
	/*
	 *	TWI
	 */
	( (TWI_S*)TWI_BASE_ADDR ) ->TWI_IDR = tmp;

	/*
	 *	SPI
	 */

	( (SPI_S*)SPI_BASE_ADDR ) ->SPI_IDR = tmp;
	AT91_PDC_Close( &( ( (SPI_S*)SPI_BASE_ADDR ) ->SPI_PDC ) );

	
	/*
	 *	SSC 0-2
	 */
	( (SSC_S*)SSC0_BASE_ADDR ) ->SSC_IDR = tmp;
	( (SSC_S*)SSC1_BASE_ADDR ) ->SSC_IDR = tmp;
	( (SSC_S*)SSC2_BASE_ADDR ) ->SSC_IDR = tmp;
	AT91_PDC_Close( &( ( (SSC_S*)SSC0_BASE_ADDR ) ->SSC_PDC ) );
	AT91_PDC_Close( &( ( (SSC_S*)SSC1_BASE_ADDR ) ->SSC_PDC ) );
	AT91_PDC_Close( &( ( (SSC_S*)SSC2_BASE_ADDR ) ->SSC_PDC ) );

	
	/*
	 *	TC 0 - 6
	 */
	( (TimerCounter*)TIMER0_BASE_ADDR ) ->TC_IDR = tmp;
	( (TimerCounter*)TIMER1_BASE_ADDR ) ->TC_IDR = tmp;
	( (TimerCounter*)TIMER2_BASE_ADDR ) ->TC_IDR = tmp;
	( (TimerCounter*)TIMER3_BASE_ADDR ) ->TC_IDR = tmp;
	( (TimerCounter*)TIMER4_BASE_ADDR ) ->TC_IDR = tmp;