enc.cmp

来自「一本老师推荐的经典的VHDL覆盖基础的入门书籍」· CMP 代码 · 共 42 行

-- Generated by ed8b10b 1.4.0 [Altera, IP Toolbench v1.2.3 build12]
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
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component ENC
	PORT (
		clk	: IN STD_LOGIC;
		reset_n	: IN STD_LOGIC;
		idle_ins	: IN STD_LOGIC;
		kin	: IN STD_LOGIC;
		ena	: IN STD_LOGIC;
		datain	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		rdin	: IN STD_LOGIC;
		rdforce	: IN STD_LOGIC;
		kerr	: OUT STD_LOGIC;
		dataout	: OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
		valid	: OUT STD_LOGIC;
		rdout	: OUT STD_LOGIC;
		rdcascade	: OUT STD_LOGIC
	);
end component;