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来自「一本老师推荐的经典的VHDL覆盖基础的入门书籍」· 代码 · 共 809 行 · 第 1/5 页

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#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(431): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(469): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(509): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(549): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(587): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(625): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(661): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(690): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(727): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(764): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(801): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(838): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(875): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(912): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(956): Instantiation of 'stratix_lcell' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(985): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1022): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1059): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1096): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1133): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1170): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1207): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1246): Instantiation of 'stratix_ram_block' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
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