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📁 一本老师推荐的经典的VHDL覆盖基础的入门书籍
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# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1452): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1489): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1526): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1563): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1600): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1637): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1674): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             work
# Error loading design
vlog -reportprogress 300 +optwork.pll_ram_tb -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
# Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
# 
# Top level modules:
# 	pll_ram_tb
# 
# Analyzing design...
# -- Loading module work.pll_ram_tb
# -- Loading module work.pll_ram
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(160): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(197): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(237): Module 'stratix_pll' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(385): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(431): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(469): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(509): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(549): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(587): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(625): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(661): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(690): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(727): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(764): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(801): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(838): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(875): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(912): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(956): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(985): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1022): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1059): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1096): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1133): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1170): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1207): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1246): Module 'stratix_ram_block' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1304): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1341): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1378): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1415): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1452): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1489): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1526): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1563): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1600): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1637): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1674): Module 'stratix_io' is not defined.
# Optimization failed
vlog -reportprogress 300 +optwork.pll_ram_tb -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
# Model Technology ModelSim SE vlog 5.8b Compiler 2004.01 Jan 26 2004
# 
# Top level modules:
# 	pll_ram_tb
# 
# Analyzing design...
# -- Loading module work.pll_ram_tb
# -- Loading module work.pll_ram
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(160): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(197): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(237): Module 'stratix_pll' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(385): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(431): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(469): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(509): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(549): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(587): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(625): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(661): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(690): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(727): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(764): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(801): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(838): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(875): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(912): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(956): Module 'stratix_lcell' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(985): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1022): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1059): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1096): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1133): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1170): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1207): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1246): Module 'stratix_ram_block' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1304): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1341): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1378): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1415): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1452): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1489): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1526): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1563): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1600): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1637): Module 'stratix_io' is not defined.
# ** Error: D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(1674): Module 'stratix_io' is not defined.
# Optimization failed
vsim -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb
# vsim -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix -L C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb -sdftyp /=D:/prj_D/modelsim_demo/timing_sim/pll_ram_v.sdo work.pll_ram_tb 
# Loading work.pll_ram_tb
# Loading work.pll_ram
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(160): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(197): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(237): Instantiation of 'stratix_pll' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altgxb
#             work
# ** Error: (vsim-3033) D:/prj_D/modelsim_demo/timing_sim/pll_ram.vo(385): Instantiation of 'stratix_io' failed. The design unit was not found.
#         Region: /pll_ram_tb/pll_ram_u1
#         Searched libraries:
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/altera_mf
#             C:/Downloads/modelsim_oem_57e_q40_sp1_pc_models/altera/verilog/hcstratix
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