_primary.vhd

来自「一本老师推荐的经典的VHDL覆盖基础的入门书籍」· VHDL 代码 · 共 7 行

library verilog;
use verilog.vl_types.all;
entity prim_dffe is
    // This module cannot be connected to from
    // VHDL because it has unnamed ports.
end prim_dffe;