hdl_demo.vqm

一本老师推荐的经典的VHDL覆盖基础的入门书籍

defparam un4_outp_add2_Z.cin_used="true";
defparam un4_outp_add2_Z.operation_mode="arithmetic";
defparam un4_outp_add2_Z.output_mode="comb_only";
defparam un4_outp_add2_Z.lut_mask="69d4";
defparam un4_outp_add2_Z.synch_mode="off";
defparam un4_outp_add2_Z.sum_lutc_input="cin";
// @1:13
  stratix_lcell un4_outp_add1_Z (
	.combout(un4_outp_add1),
	.cout(un4_outp_carry_1),
	.dataa(accum_b_c_1),
	.datab(accum_a_c_1),
	.cin(un4_outp_carry_0)
);
defparam un4_outp_add1_Z.cin_used="true";
defparam un4_outp_add1_Z.operation_mode="arithmetic";
defparam un4_outp_add1_Z.output_mode="comb_only";
defparam un4_outp_add1_Z.lut_mask="69d4";
defparam un4_outp_add1_Z.synch_mode="off";
defparam un4_outp_add1_Z.sum_lutc_input="cin";
// @1:13
  stratix_lcell un4_outp_add0_Z (
	.combout(un4_outp_add0),
	.cout(un4_outp_carry_0),
	.dataa(accum_b_c_0),
	.datab(accum_a_c_0)
);
defparam un4_outp_add0_Z.operation_mode="arithmetic";
defparam un4_outp_add0_Z.output_mode="comb_only";
defparam un4_outp_add0_Z.lut_mask="66dd";
defparam un4_outp_add0_Z.synch_mode="off";
defparam un4_outp_add0_Z.sum_lutc_input="datac";
// @1:12
  stratix_lcell outp_1_add7_Z (
	.combout(outp_1_add7),
	.dataa(accum_a_c_7),
	.datab(accum_b_c_7),
	.cin(outp_1_carry_6)
);
defparam outp_1_add7_Z.cin_used="true";
defparam outp_1_add7_Z.operation_mode="normal";
defparam outp_1_add7_Z.output_mode="comb_only";
defparam outp_1_add7_Z.lut_mask="9696";
defparam outp_1_add7_Z.synch_mode="off";
defparam outp_1_add7_Z.sum_lutc_input="cin";
// @1:12
  stratix_lcell outp_1_add6_Z (
	.combout(outp_1_add6),
	.cout(outp_1_carry_6),
	.dataa(accum_a_c_6),
	.datab(accum_b_c_6),
	.cin(outp_1_carry_5)
);
defparam outp_1_add6_Z.cin_used="true";
defparam outp_1_add6_Z.operation_mode="arithmetic";
defparam outp_1_add6_Z.output_mode="comb_only";
defparam outp_1_add6_Z.lut_mask="96e8";
defparam outp_1_add6_Z.synch_mode="off";
defparam outp_1_add6_Z.sum_lutc_input="cin";
// @1:12
  stratix_lcell outp_1_add5_Z (
	.combout(outp_1_add5),
	.cout(outp_1_carry_5),
	.dataa(accum_a_c_5),
	.datab(accum_b_c_5),
	.cin(outp_1_carry_4)
);
defparam outp_1_add5_Z.cin_used="true";
defparam outp_1_add5_Z.operation_mode="arithmetic";
defparam outp_1_add5_Z.output_mode="comb_only";
defparam outp_1_add5_Z.lut_mask="96e8";
defparam outp_1_add5_Z.synch_mode="off";
defparam outp_1_add5_Z.sum_lutc_input="cin";
// @1:12
  stratix_lcell outp_1_add4_Z (
	.combout(outp_1_add4),
	.cout(outp_1_carry_4),
	.dataa(accum_a_c_4),
	.datab(accum_b_c_4),
	.cin(outp_1_carry_3)
);
defparam outp_1_add4_Z.cin_used="true";
defparam outp_1_add4_Z.operation_mode="arithmetic";
defparam outp_1_add4_Z.output_mode="comb_only";
defparam outp_1_add4_Z.lut_mask="96e8";
defparam outp_1_add4_Z.synch_mode="off";
defparam outp_1_add4_Z.sum_lutc_input="cin";
// @1:12
  stratix_lcell outp_1_add3_Z (
	.combout(outp_1_add3),
	.cout(outp_1_carry_3),
	.dataa(accum_a_c_3),
	.datab(accum_b_c_3),
	.cin(outp_1_carry_2)
);
defparam outp_1_add3_Z.cin_used="true";
defparam outp_1_add3_Z.operation_mode="arithmetic";
defparam outp_1_add3_Z.output_mode="comb_only";
defparam outp_1_add3_Z.lut_mask="96e8";
defparam outp_1_add3_Z.synch_mode="off";
defparam outp_1_add3_Z.sum_lutc_input="cin";
// @1:12
  stratix_lcell outp_1_add2_Z (
	.combout(outp_1_add2),
	.cout(outp_1_carry_2),
	.dataa(accum_a_c_2),
	.datab(accum_b_c_2),
	.cin(outp_1_carry_1)
);
defparam outp_1_add2_Z.cin_used="true";
defparam outp_1_add2_Z.operation_mode="arithmetic";
defparam outp_1_add2_Z.output_mode="comb_only";
defparam outp_1_add2_Z.lut_mask="96e8";
defparam outp_1_add2_Z.synch_mode="off";
defparam outp_1_add2_Z.sum_lutc_input="cin";
// @1:12
  stratix_lcell outp_1_add1_Z (
	.combout(outp_1_add1),
	.cout(outp_1_carry_1),
	.dataa(accum_a_c_1),
	.datab(accum_b_c_1),
	.cin(outp_1_carry_0)
);
defparam outp_1_add1_Z.cin_used="true";
defparam outp_1_add1_Z.operation_mode="arithmetic";
defparam outp_1_add1_Z.output_mode="comb_only";
defparam outp_1_add1_Z.lut_mask="96e8";
defparam outp_1_add1_Z.synch_mode="off";
defparam outp_1_add1_Z.sum_lutc_input="cin";
// @1:12
  stratix_lcell outp_1_add0_Z (
	.combout(outp_1_add0),
	.cout(outp_1_carry_0),
	.dataa(accum_a_c_0),
	.datab(accum_b_c_0)
);
defparam outp_1_add0_Z.operation_mode="arithmetic";
defparam outp_1_add0_Z.output_mode="comb_only";
defparam outp_1_add0_Z.lut_mask="6688";
defparam outp_1_add0_Z.synch_mode="off";
defparam outp_1_add0_Z.sum_lutc_input="datac";
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* alu */

module hdl_demo (
  rst,
  clk,
  start_value,
  in_a,
  in_b,
  in_c,
  accum_a,
  accum_b,
  result
);
input rst ;
input clk ;
input [31:0] start_value ;
input in_a ;
input in_b ;
input in_c ;
input [7:0] accum_a ;
input [7:0] accum_b ;
output [7:0] result /* synthesis syn_tristate = 1 */;
wire rst ;
wire clk ;
wire in_a ;
wire in_b ;
wire in_c ;
wire [9:1] state;
wire [0:0] state_i;
wire [4:2] state_ns_0_0_a;
wire [3:3] state_ns_i_0_a;
wire [2:0] op_code;
wire [31:0] start_value_c;
wire [7:0] accum_b_c;
wire [7:0] accum_a_c;
wire [7:0] alu1_outp;
wire VCC ;
wire GND ;
wire clk_c ;
wire rst_c ;
wire start ;
wire in_c_c ;
wire in_b_c ;
wire in_a_c ;
wire start9 ;
wire start9_16 ;
wire start9_17 ;
wire start9_26 ;
wire start9_29 ;
wire start9_20 ;
wire start9_21 ;
wire start9_22 ;
wire start9_23 ;
wire start9_26_a ;
wire start9_18 ;
//@1:1
  assign VCC = 1'b1;
//@1:1
  assign GND = 1'b0;
// @2:86
  stratix_lcell state_9_ (
	.regout(state[9]),
	.clk(clk_c),
	.datad(state[4]),
	.aclr(rst_c),
	.ena(start)
);
defparam state_9_.operation_mode="normal";
defparam state_9_.output_mode="reg_only";
defparam state_9_.lut_mask="ff00";
defparam state_9_.synch_mode="off";
defparam state_9_.sum_lutc_input="datac";
// @2:77
  stratix_lcell state_8_ (
	.regout(state[8]),
	.clk(clk_c),
	.datad(state[3]),
	.aclr(rst_c),
	.ena(start)
);
defparam state_8_.operation_mode="normal";
defparam state_8_.output_mode="reg_only";
defparam state_8_.lut_mask="ff00";
defparam state_8_.synch_mode="off";
defparam state_8_.sum_lutc_input="datac";
// @2:68
  stratix_lcell state_7_ (
	.regout(state[7]),
	.clk(clk_c),
	.datad(state[2]),
	.aclr(rst_c),
	.ena(start)
);
defparam state_7_.operation_mode="normal";
defparam state_7_.output_mode="reg_only";
defparam state_7_.lut_mask="ff00";
defparam state_7_.synch_mode="off";
defparam state_7_.sum_lutc_input="datac";
// @2:59
  stratix_lcell state_6_ (
	.regout(state[6]),
	.clk(clk_c),
	.datad(state[1]),
	.aclr(rst_c),
	.ena(start)
);
defparam state_6_.operation_mode="normal";
defparam state_6_.output_mode="reg_only";
defparam state_6_.lut_mask="ff00";
defparam state_6_.synch_mode="off";
defparam state_6_.sum_lutc_input="datac";
// @2:50
  stratix_lcell state_5_ (
	.regout(state[5]),
	.clk(clk_c),
	.dataa(state_i[0]),
	.aclr(rst_c),
	.ena(start)
);
defparam state_5_.operation_mode="normal";
defparam state_5_.output_mode="reg_only";
defparam state_5_.lut_mask="5555";
defparam state_5_.synch_mode="off";
defparam state_5_.sum_lutc_input="datac";
// @2:83
  stratix_lcell state_4_ (
	.regout(state[4]),
	.clk(clk_c),
	.dataa(state[9]),
	.datab(in_c_c),
	.datac(in_b_c),
	.datad(state_ns_0_0_a[4]),
	.aclr(rst_c),
	.ena(start)
);
defparam state_4_.operation_mode="normal";
defparam state_4_.output_mode="reg_only";
defparam state_4_.lut_mask="aaae";
defparam state_4_.synch_mode="off";
defparam state_4_.sum_lutc_input="datac";
// @2:74
  stratix_lcell state_3_ (
	.regout(state[3]),
	.clk(clk_c),
	.dataa(state[8]),
	.datab(state[7]),
	.datac(in_c_c),
	.datad(state_ns_i_0_a[3]),
	.aclr(rst_c),
	.ena(start)
);
defparam state_3_.operation_mode="normal";
defparam state_3_.output_mode="reg_only";
defparam state_3_.lut_mask="4aea";
defparam state_3_.synch_mode="off";
defparam state_3_.sum_lutc_input="datac";
// @2:65
  stratix_lcell state_2_ (
	.regout(state[2]),
	.clk(clk_c),
	.dataa(state[7]),
	.datab(state[6]),
	.datac(in_c_c),
	.datad(state_ns_0_0_a[2]),
	.aclr(rst_c),
	.ena(start)
);
defparam state_2_.operation_mode="normal";
defparam state_2_.output_mode="reg_only";
defparam state_2_.lut_mask="ce0a";
defparam state_2_.synch_mode="off";
defparam state_2_.sum_lutc_input="datac";
// @2:56
  stratix_lcell state_1_ (
	.regout(state[1]),
	.clk(clk_c),
	.dataa(state[5]),
	.datab(state[6]),
	.datac(in_b_c),
	.datad(in_a_c),
	.aclr(rst_c),
	.ena(start)
);
defparam state_1_.operation_mode="normal";
defparam state_1_.output_mode="reg_only";
defparam state_1_.lut_mask="ee0c";
defparam state_1_.synch_mode="off";
defparam state_1_.sum_lutc_input="datac";
// @2:47
  stratix_lcell state_i_0_ (
	.regout(state_i[0]),
	.clk(clk_c),
	.dataa(state[5]),
	.datab(in_a_c),
	.aclr(rst_c),
	.ena(start)
);
defparam state_i_0_.operation_mode="normal";
defparam state_i_0_.output_mode="reg_only";
defparam state_i_0_.lut_mask="dddd";
defparam state_i_0_.synch_mode="off";
defparam state_i_0_.sum_lutc_input="datac";
// @2:38
  stratix_lcell op_code_2_ (
	.regout(op_code[2]),
	.clk(clk_c),
	.dataa(state[9]),
	.datab(state[4]),
	.aclr(rst_c),
	.ena(start)
);
defparam op_code_2_.operation_mode="normal";
defparam op_code_2_.output_mode="reg_only";
defparam op_code_2_.lut_mask="eeee";
defparam op_code_2_.synch_mode="off";
defparam op_code_2_.sum_lutc_input="datac";
// @2:38
  stratix_lcell op_code_1_ (
	.regout(op_code[1]),
	.clk(clk_c),
	.dataa(state[2]),
	.datab(state[3]),
	.datac(state[7]),
	.datad(state[8]),
	.aclr(rst_c),
	.ena(start)
);
defparam op_code_1_.operation_mode="normal";
defparam op_code_1_.output_mode="reg_only";
defparam op_code_1_.lut_mask="fffe";
defparam op_code_1_.synch_mode="off";
defparam op_code_1_.sum_lutc_input="datac";
// @2:38
  stratix_lcell op_code_0_ (
	.regout(op_code[0]),
	.clk(clk_c),
	.dataa(state[1]),
	.datab(state[6]),
	.datac(state[3]),
	.datad(state[8]),
	.aclr(rst_c),
	.ena(start)
);
defparam op_code_0_.operation_mode="normal";
defparam op_code_0_.output_mode="reg_only";
defparam op_code_0_.lut_mask="fffe";
defparam op_code_0_.synch_mode="off";
defparam op_code_0_.sum_lutc_input="datac";
// @2:33
  stratix_lcell start_Z (
	.regout(start),
	.clk(clk_c),
	.datad(VCC),
	.aclr(rst_c),
	.ena(start9)
);
defparam start_Z.operation_mode="normal";
defparam start_Z.output_mode="reg_only";
defparam start_Z.lut_mask="ff00";
defparam start_Z.synch_mode="off";
defparam start_Z.sum_lutc_input="datac";
// @2:36
  stratix_lcell start9_Z (
	.combout(start9),
	.dataa(start9_16),
	.datab(start9_17),
	.datac(start9_26),
	.datad(start9_29)
);
defparam start9_Z.operation_mode="normal";
defparam start9_Z.output_mode="comb_only";
defparam start9_Z.lut_mask="8000";
defparam start9_Z.synch_mode="off";
defparam start9_Z.sum_lutc_input="datac";
// @2:36
  stratix_lcell start9_29_Z (
	.combout(start9_29),
	.dataa(start9_20),
	.datab(start9_21),
	.datac(start9_22),
	.datad(start9_23)
);
defparam start9_29_Z.operation_mode="normal";
defparam start9_29_Z.output_mode="comb_only";
defparam start9_29_Z.lut_mask="8000";
defparam start9_29_Z.synch_mode="off";
defparam start9_29_Z.sum_lutc_input="datac";
// @2:36
  stratix_lcell start9_26_Z (
	.combout(start9_26),
	.dataa(start_value_c[14]),
	.datab(start_value_c[13]),
	.datac(start9_26_a),
	.datad(start9_18)
);
defparam start9_26_Z.operation_mode="normal";
defparam start9_26_Z.output_mode="comb_only";
defparam start9_26_Z.lut_mask="0800";
defparam start9_26_Z.synch_mode="off";
defparam start9_26_Z.sum_lutc_input="datac";
// @2:36
  stratix_lcell start9_26_a_Z (
	.combout(start9_26_a),
	.datac(start_value_c[15]),
	.datad(start_value_c[16])
);
defparam start9_26_a_Z.operation_mode="normal";
defparam start9_26_a_Z.output_mode="comb_only";
defparam start9_26_a_Z.lut_mask="0fff";
defparam start9_26_a_Z.synch_mode="off";
defparam start9_26_a_Z.sum_lutc_input="datac";
// @2:38
  stratix_lcell state_ns_i_0_a_3_ (
	.combout(state_ns_i_0_a[3]),
	.dataa(in_b_c),
	.datab(in_a_c)
);
defparam state_ns_i_0_a_3_.operation_mode="normal";
defparam state_ns_i_0_a_3_.output_mode="comb_only";
defparam state_ns_i_0_a_3_.lut_mask="4444";
defparam state_ns_i_0_a_3_.synch_mode="off";
defparam state_ns_i_0_a_3_.sum_lutc_input="datac";
// @2:38
  stratix_lcell state_ns_0_0_a_4_ (
	.combout(state_ns_0_0_a[4]),
	.dataa(state[8]),
	.datab(in_a_c)
);
defparam state_ns_0_0_a_4_.operation_mode="normal";
defparam state_ns_0_0_a_4_.output_mode="comb_only";
defparam state_ns_0_0_a_4_.lut_mask="7777";
defparam state_ns_0_0_a_4_.synch_mode="off";
defparam state_ns_0_0_a_4_.sum_lutc_input="datac";
// @2:38
  stratix_lcell state_ns_0_0_a_2_ (
	.combout(state_ns_0_0_a[2]),
	.dataa(in_b_c),
	.datab(in_a_c)
);
defparam state_ns_0_0_a_2_.operation_mode="normal";
defparam state_ns_0_0_a_2_.output_mode="comb_only";
defparam state_ns_0_0_a_2_.lut_mask="2222";
defparam state_ns_0_0_a_2_.synch_mode="off";
defparam state_ns_0_0_a_2_.sum_lutc_input="datac";
// @2:36
  stratix_lcell start9_23_Z (
	.combout(start9_23),
	.dataa(start_value_c[7]),
	.datab(start_value_c[8]),
	.datac(start_value_c[17]),
	.datad(start_value_c[19])
);
defparam start9_23_Z.operation_mode="normal";
defparam start9_23_Z.output_mode="comb_only";
defparam start9_23_Z.lut_mask="0001";
defparam start9_23_Z.synch_mode="off";
defparam start9_23_Z.sum_lutc_input="datac";
// @2:36
  stratix_lcell start9_22_Z (
	.combout(start9_22),
	.dataa(start_value_c[21]),
	.datab(start_value_c[22]),
	.datac(start_value_c[28]),
	.datad(start_value_c[30])
);
defparam start9_22_Z.operation_mode="normal";
defparam start9_22_Z.output_mode="comb_only";
defparam start9_22_Z.lut_mask="0001";
defparam start9_22_Z.synch_mode="off";
defparam start9_22_Z.sum_lutc_input="datac";
// @2:36
  stratix_lcell start9_21_Z (
	.combout(start9_21),
	.dataa(start_value_c[25]),
	.datab(start_value_c[26]),
	.datac(start_value_c[27]),
	.datad(start_value_c[29])