📄 hdl_demo.srr
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Starting Arrival
Instance Reference Type Pin Net Time Slack
Clock
-------------------------------------------------------------------------------------------------------
alu1.outp[0] hdl_demo|clk stratix_lcell_ff regout outp_0 5.156 -5.041
alu1.outp[1] hdl_demo|clk stratix_lcell_ff regout outp_1 5.156 -5.041
alu1.outp[2] hdl_demo|clk stratix_lcell_ff regout outp_2 5.156 -5.041
alu1.outp[3] hdl_demo|clk stratix_lcell_ff regout outp_3 5.156 -5.041
alu1.outp[4] hdl_demo|clk stratix_lcell_ff regout outp_4 5.156 -5.041
alu1.outp[5] hdl_demo|clk stratix_lcell_ff regout outp_5 5.156 -5.041
alu1.outp[6] hdl_demo|clk stratix_lcell_ff regout outp_6 5.156 -5.041
alu1.outp[7] hdl_demo|clk stratix_lcell_ff regout outp_7 5.156 -5.041
accum_a[7:0] hdl_demo|clk Port accum_a[0] accum_a[0] 2.000 -0.469
accum_b[7:0] hdl_demo|clk Port accum_b[0] accum_b[0] 2.000 -0.450
=======================================================================================================
Ending Points with Worst Slack
******************************
Starting Required
Instance Reference Type Pin Net Time Slack
Clock
--------------------------------------------------------------------------------------------------------
result[7:0] hdl_demo|clk Port result[0] result[0] 4.667 -5.041
result[7:0] hdl_demo|clk Port result[1] result[1] 4.667 -5.041
result[7:0] hdl_demo|clk Port result[2] result[2] 4.667 -5.041
result[7:0] hdl_demo|clk Port result[3] result[3] 4.667 -5.041
result[7:0] hdl_demo|clk Port result[4] result[4] 4.667 -5.041
result[7:0] hdl_demo|clk Port result[5] result[5] 4.667 -5.041
result[7:0] hdl_demo|clk Port result[6] result[6] 4.667 -5.041
result[7:0] hdl_demo|clk Port result[7] result[7] 4.667 -5.041
alu1.outp[7] hdl_demo|clk stratix_lcell_ff datad outp_8_3[7] 6.423 -0.469
alu1.outp[6] hdl_demo|clk stratix_lcell_ff datad outp_8_3[6] 6.423 -0.435
========================================================================================================
Worst Path Information
***********************
Path information for path number 1:
Requested Period: 6.667
- User constraint on ending point: 2.000
= Required time: 4.667
- Propagation time: 9.708
= Slack (critical) : -5.041
Number of logic level(s): 1
Starting point: alu1.outp[0] / regout
Ending point: result[7:0] / result[0]
The start point is clocked by hdl_demo|clk [rising] on pin clk
The end point is clocked by hdl_demo|clk [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------
alu1.outp[0] stratix_lcell_ff regout Out 5.156 5.156 -
outp_0 Net - - 1.608 - 1
result_out[0] stratix_io datain In - 6.764 -
result_out[0] stratix_io padio Out 2.944 9.708 -
result[0] Net - - 0.000 - 0
result[7:0] Port result[0] Out - 9.708 -
==============================================================================================
Total path delay (propagation time + setup) of 9.708 is 8.100(83.4%) logic and 1.608(16.6%) route.
Path information for path number 2:
Requested Period: 6.667
- User constraint on ending point: 2.000
= Required time: 4.667
- Propagation time: 9.708
= Slack (critical) : -5.041
Number of logic level(s): 1
Starting point: alu1.outp[1] / regout
Ending point: result[7:0] / result[1]
The start point is clocked by hdl_demo|clk [rising] on pin clk
The end point is clocked by hdl_demo|clk [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------
alu1.outp[1] stratix_lcell_ff regout Out 5.156 5.156 -
outp_1 Net - - 1.608 - 1
result_out[1] stratix_io datain In - 6.764 -
result_out[1] stratix_io padio Out 2.944 9.708 -
result[1] Net - - 0.000 - 0
result[7:0] Port result[1] Out - 9.708 -
==============================================================================================
Total path delay (propagation time + setup) of 9.708 is 8.100(83.4%) logic and 1.608(16.6%) route.
Path information for path number 3:
Requested Period: 6.667
- User constraint on ending point: 2.000
= Required time: 4.667
- Propagation time: 9.708
= Slack (critical) : -5.041
Number of logic level(s): 1
Starting point: alu1.outp[2] / regout
Ending point: result[7:0] / result[2]
The start point is clocked by hdl_demo|clk [rising] on pin clk
The end point is clocked by hdl_demo|clk [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------
alu1.outp[2] stratix_lcell_ff regout Out 5.156 5.156 -
outp_2 Net - - 1.608 - 1
result_out[2] stratix_io datain In - 6.764 -
result_out[2] stratix_io padio Out 2.944 9.708 -
result[2] Net - - 0.000 - 0
result[7:0] Port result[2] Out - 9.708 -
==============================================================================================
Total path delay (propagation time + setup) of 9.708 is 8.100(83.4%) logic and 1.608(16.6%) route.
Path information for path number 4:
Requested Period: 6.667
- User constraint on ending point: 2.000
= Required time: 4.667
- Propagation time: 9.708
= Slack (critical) : -5.041
Number of logic level(s): 1
Starting point: alu1.outp[3] / regout
Ending point: result[7:0] / result[3]
The start point is clocked by hdl_demo|clk [rising] on pin clk
The end point is clocked by hdl_demo|clk [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------
alu1.outp[3] stratix_lcell_ff regout Out 5.156 5.156 -
outp_3 Net - - 1.608 - 1
result_out[3] stratix_io datain In - 6.764 -
result_out[3] stratix_io padio Out 2.944 9.708 -
result[3] Net - - 0.000 - 0
result[7:0] Port result[3] Out - 9.708 -
==============================================================================================
Total path delay (propagation time + setup) of 9.708 is 8.100(83.4%) logic and 1.608(16.6%) route.
Path information for path number 5:
Requested Period: 6.667
- User constraint on ending point: 2.000
= Required time: 4.667
- Propagation time: 9.708
= Slack (critical) : -5.041
Number of logic level(s): 1
Starting point: alu1.outp[4] / regout
Ending point: result[7:0] / result[4]
The start point is clocked by hdl_demo|clk [rising] on pin clk
The end point is clocked by hdl_demo|clk [rising]
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
----------------------------------------------------------------------------------------------
alu1.outp[4] stratix_lcell_ff regout Out 5.156 5.156 -
outp_4 Net - - 1.608 - 1
result_out[4] stratix_io datain In - 6.764 -
result_out[4] stratix_io padio Out 2.944 9.708 -
result[4] Net - - 0.000 - 0
result[7:0] Port result[4] Out - 9.708 -
==============================================================================================
Total path delay (propagation time + setup) of 9.708 is 8.100(83.4%) logic and 1.608(16.6%) route.
##### END OF TIMING REPORT #####]
Timing constraint (from p:rst to p:result[7:0]) (false path) never applies in design
Timing constraint (from i:op_code[2:0] to p:result[7:0]) (max delay 10.000000) never applies in design
##### START OF AREA REPORT #####[
Design view:work.hdl_demo(verilog)
Selecting part EP1S10F780C5
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
I/O ATOMs: 61
Total LUTs: 68 of 10570 ( 0%)
Logic resources: 68 ATOMs of 10570 ( 0%)
ATOM count by mode:
normal: 54
arithmetic: 14
DSP Blocks: 0 (0 nine-bit DSP elements).
DSP Utilization: 0.00% of available 6 blocks (48 nine-bit).
ShiftTap: 0 (0 registers)
MRAM: 0 (0% of 1)
M4Ks: 0 (0% of 60)
M512s: 0 (0% of 94)
Total ESB: 0 bits
ATOMs using regout pin: 22
also using enable pin: 14
also using combout pin: 0
ATOMs using combout pin: 46
Number of Inputs on ATOMs: 265
Number of Nets: 228
##### END OF AREA REPORT #####]
Mapper successful!
Process took 0h:0m:1s realtime, 0h:0m:1s cputime
###########################################################]
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