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Path information for path number 1: 
    Requested Period:                        0.932
    - Setup time:                            0.449
    = Required time:                         0.483

    - Propagation time:                      0.648
    = Slack (critical) :                     -0.164

    Number of logic level(s):                0
    Starting point:                          rotate_1.q[0] / regout
    Ending point:                            rotate_1.q[1] / datab
    The start point is clocked by            top|clk [rising] on pin clk
    The end   point is clocked by            top|clk [rising] on pin clk

Instance / Net                          Pin        Pin               Arrival     No. of    
Name               Type                 Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
rotate_1.q[0]      stratix_lcell_ff     regout     Out     0.156     0.156       -         
q_0                Net                  -          -       0.492     -           2         
rotate_1.q[1]      stratix_lcell_ff     datab      In      -         0.648       -         
===========================================================================================
Total path delay (propagation time + setup) of 1.096 is 0.605(55.2%) logic and 0.492(44.8%) route.


Path information for path number 2: 
    Requested Period:                        0.932
    - Setup time:                            0.449
    = Required time:                         0.483

    - Propagation time:                      0.648
    = Slack (critical) :                     -0.164

    Number of logic level(s):                0
    Starting point:                          rotate_1.q[1] / regout
    Ending point:                            rotate_1.q[2] / datab
    The start point is clocked by            top|clk [rising] on pin clk
    The end   point is clocked by            top|clk [rising] on pin clk

Instance / Net                          Pin        Pin               Arrival     No. of    
Name               Type                 Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
rotate_1.q[1]      stratix_lcell_ff     regout     Out     0.156     0.156       -         
q_1                Net                  -          -       0.492     -           2         
rotate_1.q[2]      stratix_lcell_ff     datab      In      -         0.648       -         
===========================================================================================
Total path delay (propagation time + setup) of 1.096 is 0.605(55.2%) logic and 0.492(44.8%) route.


Path information for path number 3: 
    Requested Period:                        0.932
    - Setup time:                            0.449
    = Required time:                         0.483

    - Propagation time:                      0.648
    = Slack (critical) :                     -0.164

    Number of logic level(s):                0
    Starting point:                          rotate_1.q[2] / regout
    Ending point:                            rotate_1.q[3] / datab
    The start point is clocked by            top|clk [rising] on pin clk
    The end   point is clocked by            top|clk [rising] on pin clk

Instance / Net                          Pin        Pin               Arrival     No. of    
Name               Type                 Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
rotate_1.q[2]      stratix_lcell_ff     regout     Out     0.156     0.156       -         
q_2                Net                  -          -       0.492     -           2         
rotate_1.q[3]      stratix_lcell_ff     datab      In      -         0.648       -         
===========================================================================================
Total path delay (propagation time + setup) of 1.096 is 0.605(55.2%) logic and 0.492(44.8%) route.


Path information for path number 4: 
    Requested Period:                        0.932
    - Setup time:                            0.449
    = Required time:                         0.483

    - Propagation time:                      0.648
    = Slack (critical) :                     -0.164

    Number of logic level(s):                0
    Starting point:                          rotate_1.q[3] / regout
    Ending point:                            rotate_1.q[4] / datab
    The start point is clocked by            top|clk [rising] on pin clk
    The end   point is clocked by            top|clk [rising] on pin clk

Instance / Net                          Pin        Pin               Arrival     No. of    
Name               Type                 Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
rotate_1.q[3]      stratix_lcell_ff     regout     Out     0.156     0.156       -         
q_3                Net                  -          -       0.492     -           2         
rotate_1.q[4]      stratix_lcell_ff     datab      In      -         0.648       -         
===========================================================================================
Total path delay (propagation time + setup) of 1.096 is 0.605(55.2%) logic and 0.492(44.8%) route.


Path information for path number 5: 
    Requested Period:                        0.932
    - Setup time:                            0.449
    = Required time:                         0.483

    - Propagation time:                      0.648
    = Slack (critical) :                     -0.164

    Number of logic level(s):                0
    Starting point:                          rotate_1.q[4] / regout
    Ending point:                            rotate_1.q[5] / datab
    The start point is clocked by            top|clk [rising] on pin clk
    The end   point is clocked by            top|clk [rising] on pin clk

Instance / Net                          Pin        Pin               Arrival     No. of    
Name               Type                 Name       Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------
rotate_1.q[4]      stratix_lcell_ff     regout     Out     0.156     0.156       -         
q_4                Net                  -          -       0.492     -           2         
rotate_1.q[5]      stratix_lcell_ff     datab      In      -         0.648       -         
===========================================================================================
Total path delay (propagation time + setup) of 1.096 is 0.605(55.2%) logic and 0.492(44.8%) route.



##### END OF TIMING REPORT #####]


##### START OF AREA REPORT #####[
Design view:work.top(verilog)
Selecting part EP1S10F780C5
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..

I/O ATOMs:       28

Total LUTs:  16 of 10570 ( 0%)
Logic resources:  16 ATOMs of 10570 ( 0%)
ATOM count by mode:
  normal:       16
  arithmetic:   0

DSP Blocks:     0  (0 nine-bit DSP elements).
DSP Utilization: 0.00% of available 6 blocks (48 nine-bit).
ShiftTap:       0  (0 registers)
MRAM:           0  (0% of 1)
M4Ks:           0  (0% of 60)
M512s:          0  (0% of 94)
Total ESB:      0 bits 

ATOMs using regout pin: 16
  also using enable pin: 0
  also using combout pin: 0
ATOMs using combout pin: 0
Number of Inputs on ATOMs: 80
Number of Nets:   116

##### END OF AREA REPORT #####]

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