top1.xrf

一本老师推荐的经典的VHDL覆盖基础的入门书籍

vendor_name = Synplicity
source_file = 0, noname, synplify
source_file = 1, noname, synplify
source_file = 2, c:\eda\synplicity\synplify_751\lib\vhd\std.vhd, synplify
source_file = 3, d:\prj_d\synplify_pro\source\mixed\vhdl\mux21.vhd, synplify
source_file = 4, c:\eda\synplicity\synplify_751\lib\vhd\std1164.vhd, synplify
source_file = 5, d:\prj_d\synplify_pro\source\mixed\vhdl\top.vhd, synplify
source_file = 6, d:\prj_d\synplify_pro\source\mixed\vhdl\rotate.v, synplify
source_file = 7, d:\prj_d\synplify_pro\source\mixed\vhdl\reg8.v, synplify
source_file = 8, d:\prj_d\synplify_pro\source\mixed\vhdl\mux.v, synplify
design_name=top
instance = port, q[7:0], , top, 5, 4:7:4:7
instance = port, a[7:0], , top, 5, 5:1:5:1
instance = port, b[7:0], , top, 5, 5:4:5:4
instance = port, sel, , top, 5, 6:1:6:3
instance = port, r_l, , top, 5, 6:6:6:8
instance = port, clk, , top, 5, 6:11:6:13
instance = port, rst, , top, 5, 6:16:6:18
instance = comp, rst_in, , top, 5, 6:16:6:18
instance = comp, clk_in, , top, 5, 6:11:6:13
instance = comp, r_l_in, , top, 5, 6:6:6:8
instance = comp, sel_in, , top, 5, 6:1:6:3
instance = comp, b_in_7_, , top, 5, 5:4:5:4
instance = comp, b_in_6_, , top, 5, 5:4:5:4
instance = comp, b_in_5_, , top, 5, 5:4:5:4
instance = comp, b_in_4_, , top, 5, 5:4:5:4
instance = comp, b_in_3_, , top, 5, 5:4:5:4
instance = comp, b_in_2_, , top, 5, 5:4:5:4
instance = comp, b_in_1_, , top, 5, 5:4:5:4
instance = comp, b_in_0_, , top, 5, 5:4:5:4
instance = comp, a_in_7_, , top, 5, 5:1:5:1
instance = comp, a_in_6_, , top, 5, 5:1:5:1
instance = comp, a_in_5_, , top, 5, 5:1:5:1
instance = comp, a_in_4_, , top, 5, 5:1:5:1
instance = comp, a_in_3_, , top, 5, 5:1:5:1
instance = comp, a_in_2_, , top, 5, 5:1:5:1
instance = comp, a_in_1_, , top, 5, 5:1:5:1
instance = comp, a_in_0_, , top, 5, 5:1:5:1
instance = comp, q_out_7_, , top, 5, 4:7:4:7
instance = comp, q_out_6_, , top, 5, 4:7:4:7
instance = comp, q_out_5_, , top, 5, 4:7:4:7
instance = comp, q_out_4_, , top, 5, 4:7:4:7
instance = comp, q_out_3_, , top, 5, 4:7:4:7
instance = comp, q_out_2_, , top, 5, 4:7:4:7
instance = comp, q_out_1_, , top, 5, 4:7:4:7
instance = comp, q_out_0_, , top, 5, 4:7:4:7
instance = comp, inst3, , top, 5, 48:0:48:4
instance = comp, inst2, , top, 5, 39:0:39:4
design_name=rotate
instance = comp, q_7_, , rotate, 6, 8:0:8:5
instance = comp, q_6_, , rotate, 6, 8:0:8:5
instance = comp, q_5_, , rotate, 6, 8:0:8:5
instance = comp, q_4_, , rotate, 6, 8:0:8:5
instance = comp, q_3_, , rotate, 6, 8:0:8:5
instance = comp, q_2_, , rotate, 6, 8:0:8:5
instance = comp, q_1_, , rotate, 6, 8:0:8:5
instance = comp, q_0_, , rotate, 6, 8:0:8:5
design_name=reg8
instance = comp, q_7_, , reg8, 7, 7:0:7:5
instance = comp, q_6_, , reg8, 7, 7:0:7:5
instance = comp, q_5_, , reg8, 7, 7:0:7:5
instance = comp, q_4_, , reg8, 7, 7:0:7:5
instance = comp, q_3_, , reg8, 7, 7:0:7:5
instance = comp, q_2_, , reg8, 7, 7:0:7:5
instance = comp, q_1_, , reg8, 7, 7:0:7:5
instance = comp, q_0_, , reg8, 7, 7:0:7:5