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The start point is clocked by top|clk [rising] on pin clk
The end point is clocked by top|clk [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
inst2.q[2] stratix_lcell_ff regout Out 0.156 0.156 -
q_2 Net - - 0.804 - 2
inst2.q[3] stratix_lcell_ff datab In - 0.960 -
===========================================================================================
Total path delay (propagation time + setup) of 1.409 is 0.605(42.9%) logic and 0.804(57.1%) route.
Path information for path number 4:
Requested Period: 6.667
- Setup time: 0.449
= Required time: 6.218
- Propagation time: 0.960
= Slack (critical) : 5.258
Number of logic level(s): 0
Starting point: inst2.q[3] / regout
Ending point: inst2.q[4] / datab
The start point is clocked by top|clk [rising] on pin clk
The end point is clocked by top|clk [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
inst2.q[3] stratix_lcell_ff regout Out 0.156 0.156 -
q_3 Net - - 0.804 - 2
inst2.q[4] stratix_lcell_ff datab In - 0.960 -
===========================================================================================
Total path delay (propagation time + setup) of 1.409 is 0.605(42.9%) logic and 0.804(57.1%) route.
Path information for path number 5:
Requested Period: 6.667
- Setup time: 0.449
= Required time: 6.218
- Propagation time: 0.960
= Slack (critical) : 5.258
Number of logic level(s): 0
Starting point: inst2.q[4] / regout
Ending point: inst2.q[5] / datab
The start point is clocked by top|clk [rising] on pin clk
The end point is clocked by top|clk [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
inst2.q[4] stratix_lcell_ff regout Out 0.156 0.156 -
q_4 Net - - 0.804 - 2
inst2.q[5] stratix_lcell_ff datab In - 0.960 -
===========================================================================================
Total path delay (propagation time + setup) of 1.409 is 0.605(42.9%) logic and 0.804(57.1%) route.
Path information for path number 6:
Requested Period: 6.667
- Setup time: 0.449
= Required time: 6.218
- Propagation time: 0.960
= Slack (critical) : 5.258
Number of logic level(s): 0
Starting point: inst2.q[5] / regout
Ending point: inst2.q[6] / datab
The start point is clocked by top|clk [rising] on pin clk
The end point is clocked by top|clk [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
inst2.q[5] stratix_lcell_ff regout Out 0.156 0.156 -
q_5 Net - - 0.804 - 2
inst2.q[6] stratix_lcell_ff datab In - 0.960 -
===========================================================================================
Total path delay (propagation time + setup) of 1.409 is 0.605(42.9%) logic and 0.804(57.1%) route.
Path information for path number 7:
Requested Period: 6.667
- Setup time: 0.449
= Required time: 6.218
- Propagation time: 0.960
= Slack (critical) : 5.258
Number of logic level(s): 0
Starting point: inst2.q[6] / regout
Ending point: inst2.q[7] / datab
The start point is clocked by top|clk [rising] on pin clk
The end point is clocked by top|clk [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
inst2.q[6] stratix_lcell_ff regout Out 0.156 0.156 -
q_6 Net - - 0.804 - 2
inst2.q[7] stratix_lcell_ff datab In - 0.960 -
===========================================================================================
Total path delay (propagation time + setup) of 1.409 is 0.605(42.9%) logic and 0.804(57.1%) route.
Path information for path number 8:
Requested Period: 6.667
- Setup time: 0.449
= Required time: 6.218
- Propagation time: 0.960
= Slack (critical) : 5.258
Number of logic level(s): 0
Starting point: inst2.q[7] / regout
Ending point: inst2.q[0] / datab
The start point is clocked by top|clk [rising] on pin clk
The end point is clocked by top|clk [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
inst2.q[7] stratix_lcell_ff regout Out 0.156 0.156 -
q_7 Net - - 0.804 - 2
inst2.q[0] stratix_lcell_ff datab In - 0.960 -
===========================================================================================
Total path delay (propagation time + setup) of 1.409 is 0.605(42.9%) logic and 0.804(57.1%) route.
Path information for path number 9:
Requested Period: 6.667
- Setup time: 0.352
= Required time: 6.315
- Propagation time: 0.960
= Slack (non-critical) : 5.355
Number of logic level(s): 0
Starting point: inst3.q[0] / regout
Ending point: inst2.q[0] / datac
The start point is clocked by top|clk [rising] on pin clk
The end point is clocked by top|clk [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
inst3.q[0] stratix_lcell_ff regout Out 0.156 0.156 -
q_0 Net - - 0.804 - 1
inst2.q[0] stratix_lcell_ff datac In - 0.960 -
===========================================================================================
Total path delay (propagation time + setup) of 1.312 is 0.508(38.7%) logic and 0.804(61.3%) route.
Path information for path number 10:
Requested Period: 6.667
- Setup time: 0.352
= Required time: 6.315
- Propagation time: 0.960
= Slack (non-critical) : 5.355
Number of logic level(s): 0
Starting point: inst3.q[1] / regout
Ending point: inst2.q[1] / datac
The start point is clocked by top|clk [rising] on pin clk
The end point is clocked by top|clk [rising] on pin clk
Instance / Net Pin Pin Arrival No. of
Name Type Name Dir Delay Time Fan Out(s)
-------------------------------------------------------------------------------------------
inst3.q[1] stratix_lcell_ff regout Out 0.156 0.156 -
q_1 Net - - 0.804 - 1
inst2.q[1] stratix_lcell_ff datac In - 0.960 -
===========================================================================================
Total path delay (propagation time + setup) of 1.312 is 0.508(38.7%) logic and 0.804(61.3%) route.
##### END OF TIMING REPORT #####]
##### START OF AREA REPORT #####[
Design view:work.top(structural)
Selecting part EP1S10F780C5
@N: FA174 |The following device usage report estimates place and route data. Please look at the place and route report for final resource usage..
I/O ATOMs: 28
Total LUTs: 16 of 10570 ( 0%)
Logic resources: 16 ATOMs of 10570 ( 0%)
ATOM count by mode:
normal: 16
arithmetic: 0
DSP Blocks: 0 (0 nine-bit DSP elements).
DSP Utilization: 0.00% of available 6 blocks (48 nine-bit).
ShiftTap: 0 (0 registers)
MRAM: 0 (0% of 1)
M4Ks: 0 (0% of 60)
M512s: 0 (0% of 94)
Total ESB: 0 bits
ATOMs using regout pin: 16
also using enable pin: 0
also using combout pin: 0
ATOMs using combout pin: 0
Number of Inputs on ATOMs: 80
Number of Nets: 116
##### END OF AREA REPORT #####]
Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################]
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