📄 altera_mf_87.vhd
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end if;
end if;
end process;
-- ------------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set sign_a_reg)
-- The signal registered is signa
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if sign_reg_a is unregistered and
-- signa changes value
-- ------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, signa)
begin
if (sign_reg_a = "UNREGISTERED") then
sign_a_reg <= signa;
else
if (((sign_aclr_a= "ACLR0") and (aclr0 = '1')) or
((sign_aclr_a= "ACLR1") and (aclr1 = '1')) or
((sign_aclr_a= "ACLR2") and (aclr2 = '1')) or
((sign_aclr_a= "ACLR3") and (aclr3 = '1'))) then
sign_a_reg <= '0';
elsif (((sign_reg_a = "CLOCK0") and (clock0= '1') and clock0'event and (ena0 ='1')) or
((sign_reg_a = "CLOCK1") and (clock1= '1') and clock1'event and (ena1 ='1')) or
((sign_reg_a = "CLOCK2") and (clock2= '1') and clock2'event and (ena2 ='1')) or
((sign_reg_a = "CLOCK3") and (clock3= '1') and clock3'event and (ena3 ='1'))) then
sign_a_reg <= signa;
end if;
end if;
end process;
-- ------------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set sign_b_reg)
-- The signal registered is signb
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if sign_reg_b is unregistered and
-- signb changes value
-- ------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, signb)
begin
if sign_reg_b= "UNREGISTERED" then
sign_b_reg <= signb;
else
if (((sign_aclr_b= "ACLR0") and (aclr0 = '1')) or
((sign_aclr_b= "ACLR1") and (aclr1 = '1')) or
((sign_aclr_b= "ACLR2") and (aclr2 = '1')) or
((sign_aclr_b= "ACLR3") and (aclr3 = '1'))) then
sign_b_reg <= '0';
elsif (((sign_reg_b = "CLOCK0") and (clock0= '1') and clock0'event and (ena0 ='1')) or
((sign_reg_b = "CLOCK1") and (clock1= '1') and clock1'event and (ena1 ='1')) or
((sign_reg_b = "CLOCK2") and (clock2= '1') and clock2'event and (ena2 ='1')) or
((sign_reg_b = "CLOCK3") and (clock3= '1') and clock3'event and (ena3 ='1'))) then
sign_b_reg <= signb;
end if;
end if;
end process;
-- -------------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set sign_a_pipe)
-- The signal registered is sign_a_latent
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if sign_pipeline_reg_a
-- is unregistered and sign_a_latent changes value
-- -------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, sign_a_latent)
begin
if (sign_pipeline_reg_a = "UNREGISTERED") then
sign_a_pipe <= sign_a_latent;
else
if (((sign_pipeline_aclr_a= "ACLR0") and (aclr0 = '1')) or
((sign_pipeline_aclr_a= "ACLR1") and (aclr1 = '1')) or
((sign_pipeline_aclr_a= "ACLR2") and (aclr2 = '1')) or
((sign_pipeline_aclr_a= "ACLR3") and (aclr3 = '1'))) then
sign_a_pipe <= '0';
elsif (((sign_pipeline_reg_a = "CLOCK0") and (clock0= '1') and clock0'event and (ena0 ='1')) or
((sign_pipeline_reg_a = "CLOCK1") and (clock1= '1') and clock1'event and (ena1 ='1')) or
((sign_pipeline_reg_a = "CLOCK2") and (clock2= '1') and clock2'event and (ena2 ='1')) or
((sign_pipeline_reg_a = "CLOCK3") and (clock3= '1') and clock3'event and (ena3 ='1'))) then
sign_a_pipe <= sign_a_latent;
end if;
end if;
end process;
-- -------------------------------------------------------------------------------
-- This process contains 1 register and a combinatorial block (to set sign_b_pipe)
-- The signal registered is sign_b_latent
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if sign_pipeline_reg_b
-- is unregistered and sign_b_latent changes value
-- -------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, aclr0, aclr1, aclr2, aclr3, sign_b_latent)
begin
if (sign_pipeline_reg_b = "UNREGISTERED") then
sign_b_pipe <= sign_b_latent;
else
if (((sign_pipeline_aclr_b= "ACLR0") and (aclr0 = '1')) or
((sign_pipeline_aclr_b= "ACLR1") and (aclr1 = '1')) or
((sign_pipeline_aclr_b= "ACLR2") and (aclr2 = '1')) or
((sign_pipeline_aclr_b= "ACLR3") and (aclr3 = '1'))) then
sign_b_pipe <= '0';
elsif (((sign_pipeline_reg_b = "CLOCK0") and (clock0= '1') and clock0'event and (ena0 ='1')) or
((sign_pipeline_reg_b = "CLOCK1") and (clock1= '1') and clock1'event and (ena1 ='1')) or
((sign_pipeline_reg_b = "CLOCK2") and (clock2= '1') and clock2'event and (ena2 ='1')) or
((sign_pipeline_reg_b = "CLOCK3") and (clock3= '1') and clock3'event and (ena3 ='1'))) then
sign_b_pipe <= sign_b_latent;
end if;
end if;
end process;
-- ---------------------------------------------------------------------------------
-- This statement contains 1 register and a combinatorial block (to set accum_round_pipe_wire)
-- The signal registered is accum_round
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if accum_round_reg
-- is unregistered and accum_round changes value
-------------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, accum_round, aclr0, aclr1, aclr2, aclr3)
begin
if (accum_round_reg = "UNREGISTERED") then
accum_round_pipe_wire <= accum_round;
else
if (((accum_round_aclr = "ACLR0") and (aclr0 = '1')) or
((accum_round_aclr = "ACLR1") and (aclr1 = '1')) or
((accum_round_aclr = "ACLR2") and (aclr2 = '1')) or
((accum_round_aclr = "ACLR3") and (aclr3 = '1'))) then
accum_round_pipe_wire <= '0';
elsif (((accum_round_reg = "CLOCK0") and (clock0 = '1')
and clock0'event and (ena0 = '1')) or
((accum_round_reg = "CLOCK1") and (clock1 = '1')
and clock1'event and (ena1 = '1')) or
((accum_round_reg = "CLOCK2") and (clock2 = '1')
and clock2'event and (ena2 = '1')) or
((accum_round_reg = "CLOCK3") and (clock3 = '1')
and clock3'event and (ena3 = '1'))) then
accum_round_pipe_wire <= accum_round;
end if;
end if;
end process;
-- ---------------------------------------------------------------------------------
-- This statement contains 1 register and a combinatorial block (to set accum_round_wire)
-- The signal registered is accum_round_pipe_wire
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if accum_round_pipeline_reg
-- is unregistered and accum_round_pipe_wire changes value
-------------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, accum_round_pipe_wire, aclr0, aclr1, aclr2, aclr3)
begin
if (accum_round_pipeline_reg = "UNREGISTERED") then
accum_round_wire <= accum_round_pipe_wire;
else
if (((accum_round_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or
((accum_round_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or
((accum_round_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or
((accum_round_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then
accum_round_wire <= '0';
elsif (((accum_round_pipeline_reg = "CLOCK0") and (clock0 = '1')
and clock0'event and (ena0 = '1')) or
((accum_round_pipeline_reg = "CLOCK1") and (clock1 = '1')
and clock1'event and (ena1 = '1')) or
((accum_round_pipeline_reg = "CLOCK2") and (clock2 = '1')
and clock2'event and (ena2 = '1')) or
((accum_round_pipeline_reg = "CLOCK3") and (clock3 = '1')
and clock3'event and (ena3 = '1'))) then
accum_round_wire <= accum_round_pipe_wire;
end if;
end if;
end process;
-- ---------------------------------------------------------------------------------
-- This statement contains 1 register and a combinatorial block (to set accum_saturation_pipe_wire)
-- The signal registered is accum_saturation
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if accum_saturation_reg
-- is unregistered and accum_saturation changes value
-- ---------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, accum_saturation, aclr0, aclr1, aclr2, aclr3)
begin
if (accum_saturation_reg = "UNREGISTERED") then
accum_saturation_pipe_wire <= accum_saturation;
else
if (((accum_saturation_aclr = "ACLR0") and (aclr0 = '1')) or
((accum_saturation_aclr = "ACLR1") and (aclr1 = '1')) or
((accum_saturation_aclr = "ACLR2") and (aclr2 = '1')) or
((accum_saturation_aclr = "ACLR3") and (aclr3 = '1'))) then
accum_saturation_pipe_wire <= '0';
elsif (((accum_saturation_reg = "CLOCK0") and (clock0 = '1')
and clock0'event and (ena0 = '1')) or
((accum_saturation_reg = "CLOCK1") and (clock1 = '1')
and clock1'event and (ena1 = '1')) or
((accum_saturation_reg = "CLOCK2") and (clock2 = '1')
and clock2'event and (ena2 = '1')) or
((accum_saturation_reg = "CLOCK3") and (clock3 = '1')
and clock3'event and (ena3 = '1'))) then
accum_saturation_pipe_wire <= accum_saturation;
end if;
end if;
end process;
-- ---------------------------------------------------------------------------------
-- This statement contains 1 register and a combinatorial block (to set accum_saturate_wire)
-- The signal registered is accum_saturation_pipe_wire
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if accum_saturation_pipeline_reg
-- is unregistered and accum_saturation_pipe_wire changes value
-- ---------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, accum_saturation_pipe_wire, aclr0, aclr1, aclr2, aclr3)
begin
if (accum_saturation_pipeline_reg = "UNREGISTERED") then
accum_saturate_wire <= accum_saturation_pipe_wire;
else
if (((accum_saturation_pipeline_aclr = "ACLR0") and (aclr0 = '1')) or
((accum_saturation_pipeline_aclr = "ACLR1") and (aclr1 = '1')) or
((accum_saturation_pipeline_aclr = "ACLR2") and (aclr2 = '1')) or
((accum_saturation_pipeline_aclr = "ACLR3") and (aclr3 = '1'))) then
accum_saturate_wire <= '0';
elsif (((accum_saturation_pipeline_reg = "CLOCK0") and (clock0 = '1')
and clock0'event and (ena0 = '1')) or
((accum_saturation_pipeline_reg = "CLOCK1") and (clock1 = '1')
and clock1'event and (ena1 = '1')) or
((accum_saturation_pipeline_reg = "CLOCK2") and (clock2 = '1')
and clock2'event and (ena2 = '1')) or
((accum_saturation_pipeline_reg = "CLOCK3") and (clock3 = '1')
and clock3'event and (ena3 = '1'))) then
accum_saturate_wire <= accum_saturation_pipe_wire;
end if;
end if;
end process;
-- ---------------------------------------------------------------------------------
-- This statement contains 1 register and a combinatorial block (to set mult_round_wire)
-- The signal registered is mult_round
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if mult_round_reg
-- is unregistered and mult_round changes value
-- ---------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, mult_round, aclr0, aclr1, aclr2, aclr3)
begin
if (mult_round_reg = "UNREGISTERED") then
mult_round_wire <= mult_round;
else
if (((mult_round_aclr = "ACLR0") and (aclr0 = '1')) or
((mult_round_aclr = "ACLR1") and (aclr1 = '1')) or
((mult_round_aclr = "ACLR2") and (aclr2 = '1')) or
((mult_round_aclr = "ACLR3") and (aclr3 = '1'))) then
mult_round_wire <= '0';
elsif (((mult_round_reg = "CLOCK0") and (clock0 = '1')
and clock0'event and (ena0 = '1')) or
((mult_round_reg = "CLOCK1") and (clock1 = '1')
and clock1'event and (ena1 = '1')) or
((mult_round_reg = "CLOCK2") and (clock2 = '1')
and clock2'event and (ena2 = '1')) or
((mult_round_reg = "CLOCK3") and (clock3 = '1')
and clock3'event and (ena3 = '1'))) then
mult_round_wire <= mult_round;
end if;
end if;
end process;
-- ---------------------------------------------------------------------------------
-- This statement contains 1 register and a combinatorial block (to set mult_saturation_wire)
-- The signal registered is mult_saturation
--
-- The register has an asynchronous clear and a clock enable signal
-- NOTE: the combinatorial block is trigged if mult_saturation_reg
-- is unregistered and mult_saturation changes value
-- ---------------------------------------------------------------------------------
process (clock0, clock1, clock2, clock3, mult_saturation, ⌨️ 快捷键说明
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