📄 220model.vhd
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variable str : nstring;
begin
if (pos >= 1) then
read(str_line, str);
end if;
end;
end LPM_COMMON_CONVERSION;
-- END OF PACKAGE
---START_PACKAGE_HEADER-----------------------------------------------------
--
-- Package Name : LPM_HINT_EVALUATION
--
-- Description : Common function to grep the value of altera specific parameters
-- within the lpm_hint parameter.
--
---END_PACKAGE_HEADER--------------------------------------------------------
-- BEGINING OF PACKAGE
Library ieee;
use ieee.std_logic_1164.all;
-- PACKAGE DECLARATION
package LPM_HINT_EVALUATION is
-- FUNCTION DECLARATION
function get_parameter_value( constant given_string : string;
compare_param_name : string) return string;
end LPM_HINT_EVALUATION;
package body LPM_HINT_EVALUATION is
-- This function will search through the string (given string) to look for a match for the
-- a given parameter(compare_param_name). It will return the value for the given parameter.
function get_parameter_value( constant given_string : string;
compare_param_name : string) return string is
variable param_name_left_index : integer := given_string'length;
variable param_name_right_index : integer := given_string'length;
variable param_value_left_index : integer := given_string'length;
variable param_value_right_index : integer := given_string'length;
variable set_right_index : boolean := true;
variable extract_param_value : boolean := true;
variable extract_param_name : boolean := false;
variable param_found : boolean := false;
begin
-- checking every character of the given_string from right to left.
for i in given_string'length downto 1 loop
if (given_string(i) /= ' ') then
if (given_string(i) = '=') then
extract_param_value := false;
extract_param_name := true;
set_right_index := true;
elsif (given_string(i) = ',') then
extract_param_value := true;
extract_param_name := false;
set_right_index := true;
if (compare_param_name = given_string(param_name_left_index to param_name_right_index)) then
param_found := true; -- the compare_param_name have been found in the given_string
exit;
end if;
else
if (extract_param_value = true) then
if (set_right_index = true) then
param_value_right_index := i;
set_right_index := false;
end if;
param_value_left_index := i;
elsif (extract_param_name = true) then
if (set_right_index = true) then
param_name_right_index := i;
set_right_index := false;
end if;
param_name_left_index := i;
end if;
end if;
end if;
end loop;
-- for the case whether parameter's name is the left most part of the given_string
if (extract_param_name = true) then
if(compare_param_name = given_string(param_name_left_index to param_name_right_index)) then
param_found := true;
end if;
end if;
if(param_found = true) then
return given_string(param_value_left_index to param_value_right_index);
else
return ""; -- return empty string if parameter not found
end if;
end get_parameter_value;
end LPM_HINT_EVALUATION;
-- END OF PACKAGE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_constant
--
-- Description : Parameterized constant generator megafunction. lpm_constant
-- may be useful for convert a parameter into a constant.
--
-- Limitation : n/a
--
-- results Expected: Value specified by the argument to lpm_cvalue.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_CONSTANT is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- Width of the result[] port. (Required)
lpm_cvalue : natural; -- Constant value to be driven out on the
-- result[] port. (Required)
lpm_strength : string := "UNUSED";
lpm_type : string := "LPM_CONSTANT";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
-- // Value specified by the argument to lpm_cvalue. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_CONSTANT;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_CONSTANT is
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= conv_std_logic_vector(lpm_cvalue, lpm_width);
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_inv
--
-- Description : Parameterized inverter megafunction.
--
-- Limitation : n/a
--
-- results Expected: Inverted value of input data.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_INV is
-- GENERIC DECLARATION
generic (
lpm_width : natural; -- MUST be greater than 0
lpm_type : string := "LPM_INV";
lpm_hint : string := "UNUSED"
);
-- PORT DECLARATION
port (
data : in std_logic_vector(lpm_width-1 downto 0);
result : out std_logic_vector(lpm_width-1 downto 0)
);
end LPM_INV;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_INV is
begin
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
result <= not data;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_and
--
-- Description : Parameterized AND gate. This megafunction takes in data inputs
-- for a number of AND gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each AND gate.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity lpm_and is
generic (
-- Width of the data[][] and result[] ports. Number of AND gates. (Required)
lpm_width : natural;
-- Number of inputs to each AND gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_AND";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the AND gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Result of the AND operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0)
);
end lpm_and;
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of lpm_and is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process; -- MSG process
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) and data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
end generate L1;
end LPM_SYN;
-- END OF ARCHITECTURE
---START_ENTITY_HEADER---------------------------------------------------------
--
-- Entity Name : lpm_or
--
-- Description : Parameterized OR gate megafunction. This megafunction takes in
-- data inputs for a number of OR gates.
--
-- Limitation : n/a
--
-- results Expected: Each result[] bit is the result of each OR gate.
--
---END_ENTITY_HEADER-----------------------------------------------------------
-- LIBRARY USED----------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
-- ENTITY DECLARATION
entity LPM_OR is
generic (
-- Width of the data[] and result[] ports. Number of OR gates. (Required)
lpm_width : natural;
-- Number of inputs to each OR gate. Number of input buses. (Required)
lpm_size : natural;
lpm_type : string := "LPM_OR";
lpm_hint : string := "UNUSED"
);
port (
-- Data input to the OR gates. (Required)
data : in std_logic_2D(lpm_size-1 downto 0, lpm_width-1 downto 0);
-- Result of OR operators. (Required)
result : out std_logic_vector(lpm_width-1 downto 0));
end LPM_OR;
-- END OF ENTITY
-- BEGINNING OF ARCHITECTURE
architecture LPM_SYN of LPM_OR is
-- SIGNAL DECLARATION
signal result_int : std_logic_2d(lpm_size-1 downto 0,lpm_width-1 downto 0);
begin
-- PROCESS DECLARATION
-- basic error checking for invalid parameters
MSG: process
begin
if (lpm_width <= 0) then
ASSERT FALSE
REPORT "Value of lpm_width parameter must be greater than 0!"
SEVERITY ERROR;
end if;
if (lpm_size <= 0) then
ASSERT FALSE
REPORT "Value of lpm_size parameter must be greater than 0!"
SEVERITY ERROR;
end if;
wait;
end process MSG;
L1: for i in 0 to lpm_width-1 generate
result_int(0,i) <= data(0,i);
L2: for j in 0 to lpm_size-2 generate
result_int(j+1,i) <= result_int(j,i) or data(j+1,i);
L3: if j = lpm_size-2 generate
result(i) <= result_int(lpm_size-1,i);
end generate L3;
end generate L2;
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