📄 stratix_atoms.vhd
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--
-- VHDL Simulation Models for STRATIX Atoms
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- STRATIX_LCELL Model
--
--
library IEEE, stratix;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use stratix.atom_pack.all;
entity stratix_asynch_lcell is
generic (
lms : std_logic_vector(15 downto 0) := "1111111111111111";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_combout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_combout : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_regin : VitalDelayType01 := DefPropDelay01;
tpd_datab_regin : VitalDelayType01 := DefPropDelay01;
tpd_datac_regin : VitalDelayType01 := DefPropDelay01;
tpd_datad_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin0_regin : VitalDelayType01 := DefPropDelay01;
tpd_cin1_regin : VitalDelayType01 := DefPropDelay01;
tpd_inverta_regin : VitalDelayType01 := DefPropDelay01;
tpd_qfbkin_regin : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_inverta_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01;
tipd_inverta : VitalDelayType01 := DefPropDelay01);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
qfbkin : in std_logic := '0';
mode : in std_logic_vector(5 downto 0);
regin : out std_logic;
combout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic);
attribute VITAL_LEVEL0 of stratix_asynch_lcell : entity is TRUE;
end stratix_asynch_lcell;
architecture vital_le of stratix_asynch_lcell is
attribute VITAL_LEVEL1 of vital_le : architecture is TRUE;
signal dataa_ipd, datab_ipd : std_ulogic;
signal inverta_ipd : std_ulogic;
signal datac_ipd, datad_ipd : std_ulogic;
signal cin_ipd, cin0_ipd, cin1_ipd : std_ulogic;
-- operation_mode --> mode(0) - normal=1 arithemtic=0
-- sum_lutc_cin --> mode(1) - lutc=1 cin=0
-- sum_lutc_qfbk --> mode(2) - qfbk=1 mode1=0
-- cin_used --> mode(3) - true=1 false=0
-- cin0_used --> mode(4) - true=1 false=0
-- cin1_used --> mode(5) - true=1 false=0
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
VitalWireDelay (cin0_ipd, cin0, tipd_cin0);
VitalWireDelay (cin1_ipd, cin1, tipd_cin1);
VitalWireDelay (inverta_ipd, inverta, tipd_inverta);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd, mode,
cin_ipd, cin0_ipd, cin1_ipd, inverta_ipd, qfbkin)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
variable cout0_VitalGlitchData : VitalGlitchDataType;
variable cout1_VitalGlitchData : VitalGlitchDataType;
variable regin_VitalGlitchData : VitalGlitchDataType;
variable tmp_combout, tmp_cout, tmp_cout0, tmp_cout1, tmp_regin: std_logic;
variable lutb, cintmp : std_logic;
variable invertsig : std_logic := '0';
variable cinsel, cinsig, cin01sel, luta, lutc, lutd, datacsig: std_logic;
variable lms_var : std_logic_vector(15 downto 0) := "1111111111111111";
begin
lms_var := lms;
cinsel := (cin_ipd and mode(3)) or (inverta_ipd and (not mode(3)));
cin01sel := (cin1_ipd and cinsel) or (cin0_ipd and (not cinsel));
cintmp := (cin_ipd and mode(0)) or
((not mode(0)) and mode(3) and cin_ipd) or
((not mode(0)) and (not mode(3)) and inverta_ipd);
cinsig := (cintmp and ((not mode(4)) and (not mode(5)))) or (cin01sel and (mode(4) or mode(5)));
datacsig := (datac_ipd and mode(1)) or (cinsig and (not mode(1)));
luta := dataa_ipd XOR inverta_ipd;
lutb := datab_ipd;
lutc := (qfbkin and mode(2)) or (datacsig and (not mode(2)));
lutd := (datad_ipd and mode(0)) or (not mode(0));
tmp_combout := VitalMUX(data => lms_var,
dselect => (lutd,
lutc,
lutb,
luta));
tmp_cout0 := VitalMUX(data => lms_var,
dselect => ('0',
cin0_ipd,
lutb,
luta));
tmp_cout1 := VitalMUX(data => lms_var,
dselect => ('0',
cin1_ipd,
lutb,
luta));
tmp_cout := VitalMux2(VitalMux2(tmp_cout1, tmp_cout0, cin_ipd),
VitalMux2(tmp_cout1, tmp_cout0, inverta_ipd),
mode(3));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_combout, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_combout, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_combout, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_combout, (mode(2) = '1'))),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => regin,
OutSignalName => "REGIN",
OutTemp => tmp_combout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_regin, TRUE),
1 => (datab_ipd'last_event, tpd_datab_regin, TRUE),
2 => (datac_ipd'last_event, tpd_datac_regin, TRUE),
3 => (datad_ipd'last_event, tpd_datad_regin, TRUE),
4 => (cin_ipd'last_event, tpd_cin_regin, TRUE),
5 => (cin0_ipd'last_event, tpd_cin0_regin, TRUE),
6 => (cin1_ipd'last_event, tpd_cin1_regin, TRUE),
7 => (inverta_ipd'last_event, tpd_inverta_regin, TRUE),
8 => (qfbkin'last_event, tpd_qfbkin_regin, (mode(2) = '1'))),
GlitchData => regin_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => tmp_cout,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (cin_ipd'last_event, tpd_cin_cout, TRUE),
3 => (cin0_ipd'last_event, tpd_cin0_cout, TRUE),
4 => (cin1_ipd'last_event, tpd_cin1_cout, TRUE),
5 => (inverta_ipd'last_event, tpd_inverta_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout0,
OutSignalName => "COUT0",
OutTemp => tmp_cout0,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout0, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout0, TRUE),
2 => (cin0_ipd'last_event, tpd_cin0_cout0, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout0, TRUE)),
GlitchData => cout0_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout1,
OutSignalName => "COUT1",
OutTemp => tmp_cout1,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout1, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout1, TRUE),
2 => (cin1_ipd'last_event, tpd_cin1_cout1, TRUE),
3 => (inverta_ipd'last_event, tpd_inverta_cout1, TRUE)),
GlitchData => cout1_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_le;
library IEEE, stratix;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use stratix.atom_pack.all;
entity stratix_lcell_register is
generic (
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tsetup_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_regcascin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datac_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_regout : VitalDelayType01 := DefPropDelay01;
tpd_clk_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_qfbkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_datac_qfbkout : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_regcascin : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01);
port (clk : in std_logic := '0';
datain : in std_logic := '0';
datac : in std_logic := '0';
regcascin : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cena : in std_logic := '0';
xonv : in std_logic := '1';
smode : in std_logic := '0';
regout : out std_logic;
qfbkout : out std_logic);
attribute VITAL_LEVEL0 of stratix_lcell_register : entity is TRUE;
end stratix_lcell_register;
architecture vital_le_reg of stratix_lcell_register is
attribute VITAL_LEVEL1 of vital_le_reg : architecture is TRUE;
signal ena_ipd : std_ulogic := '1';
signal sload_ipd : std_ulogic := '0';
signal aload_ipd : std_ulogic := '0';
signal datac_ipd : std_ulogic := '0';
signal regcascin_ipd : std_ulogic := '0';
signal clk_ipd : std_ulogic := '0';
signal aclr_ipd : std_ulogic := '0';
signal sclr_ipd : std_ulogic := '0';
constant stratix_regtab : VitalStateTableType := (
-- CLK ACLR D D1 D2 EN Aload Sclr Sload Casc Synch Qp Q
( x, H, x, x, x, x, x, x, x, x, x, x, L ), -- Areset
( x, x, x, L, x, x, H, x, x, x, x, x, L ), -- Aload
( x, x, x, H, x, x, H, x, x, x, x, x, H ), -- Aload
( x, x, x, x, x, x, H, x, x, x, x, x, U ), -- Aload
( x, x, x, x, x, L, x, x, x, x, x, x, S ), -- Q=Q
( R, x, x, x, x, H, x, H, x, x, H, x, L ), -- Sreset
( R, x, x, L, x, H, x, x, H, x, H, x, L ), -- Sload
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