altera_mf_components.vhd

一本老师推荐的经典的VHDL覆盖基础的入门书籍

        uarttxd  : out   std_logic;
        uartrtsn : out   std_logic;
        uartdtrn : out   std_logic;
        uartctsn : in    std_logic := '0';
        uartdsrn : in    std_logic := '0';
        uartrxd  : in    std_logic := '0';
        uartdcdn : inout std_logic := '0';
        uartrin  : inout std_logic := '0';

        sdramclk  : out std_logic;
        sdramclkn : out std_logic;
        sdramclke : out std_logic;
        sdramwen  : out std_logic;
        sdramcasn : out std_logic;
        sdramrasn : out std_logic;
        sdramdqm  : out std_logic_vector(sdramdqm_width-1 downto 0);
        sdramaddr : out std_logic_vector(14 downto 0);
        sdramcsn  : out std_logic_vector(1 downto 0);

        sdramdq  : inout std_logic_vector(sdram_width-1 downto 0) := (others => '0');
        sdramdqs : inout std_logic_vector(sdramdqm_width-1 downto 0) := (others => '0');

        intextpin     : in  std_logic := '0';
        traceclk      : out std_logic;
        tracesync     : out std_logic;
        tracepipestat : out std_logic_vector(2 downto 0);
        tracepkt      : out std_logic_vector(15 downto 0);

        gpi           : in  std_logic_vector(gpio_width-1 downto 0) := (others => '0');
        gpo           : out std_logic_vector(gpio_width-1 downto 0));
end component;

component alt_exc_stripe
  generic
    ( processor        :       string                                   := "ARM";
      sdram_width      :       integer                                  := 32;
      sdramdqm_width   :       integer                                  := 4;
      gpio_width       :       integer                                  := 4;
      device_size      :       integer                                  := 1000;
      boot_from_flash  :       string                                   := "TRUE";
      debug_extensions :       string                                   := "TRUE";
      use_short_reset  :       string                                   := "TRUE";
      use_initialisation_files  :       string                          := "FALSE";
      dp0_mode         :       string                                   := "COMBINEDx32";
      dp1_mode         :       string                                   := "UNUSED";
      dp0_width        :       integer                                  := 32;
      dp0_widthad      :       integer                                  := 15;
      dp1_width        :       integer                                  := 32;
      dp1_widthad      :       integer                                  := 15;
      ebi0_width       :       integer                                  := 16;
      dp0_output_mode  :       string                                   := "UNREG";
      dp1_output_mode  :       string                                   := "UNREG";
      dp0_lpm_file     :       string                                   := "";
      dp1_lpm_file     :       string                                   := "";
      dp2_lpm_file     :       string                                   := "";
      dp3_lpm_file     :       string                                   := ""; 
      lpm_type         : string := "alt_exc_stripe" 
      );

  port
    ( clk_ref          : in    std_logic                                := '0';
      nreset           : inout std_logic                                := '1';
      npor             : in    std_logic                                := '1';

      proc_ntrst       : in    std_logic                                := '0';
      proc_tck         : in    std_logic                                := '0';
      proc_tdi         : in    std_logic                                := '0';
      proc_tdo         : inout std_logic                                := '0';
      proc_tms         : in    std_logic                                := '0';

      intpld           : in    std_logic_vector(5 downto 0)             := (others => '0');
      intnmi           : in    std_logic                                := '0';
      intuart          : out   std_logic;
      inttimer0        : out   std_logic;
      inttimer1        : out   std_logic;
      intcommtx        : out   std_logic;
      intcommrx        : out   std_logic;
      intproctimer     : out   std_logic;
      intprocbridge    : out   std_logic;
      perreset         : out   std_logic;

      debugrq          : in    std_logic                                := '0';
      debugext0        : in    std_logic;
      debugext1        : in    std_logic;
      debugiebrkpt     : in    std_logic                                := '0';
      debugdewpt       : in    std_logic                                := '0';
      debugack         : out   std_logic;
      debugrng0        : out   std_logic;
      debugrng1        : out   std_logic;
      debugextin       : in    std_logic_vector(3 downto 0);
      debugextout      : out   std_logic_vector(3 downto 0);

      slavehclk        : in    std_logic                                := '0';
      slavehmastlock   : in    std_logic                                := '0';
      slavehsel        : in    std_logic                                := '0';
      slavehselreg     : in    std_logic                                := '0';
      slavehreadyi     : in    std_logic                                := '0';
      slavehwrite      : in    std_logic                                := '0';
      slavehaddr       : in    std_logic_vector(31 downto 0)            := (others => '0');
      slavehburst      : in    std_logic_vector(2 downto 0)             := (others => '0');
      slavehsize       : in    std_logic_vector(1 downto 0)             := (others => '0');
      slavehtrans      : in    std_logic_vector(1 downto 0)             := (others => '0');
      slavehwdata      : in    std_logic_vector(31 downto 0)            := (others => '0');
      slavehreadyo     : out   std_logic;
      slavehrdata      : out   std_logic_vector(31 downto 0);
      slavehresp       : out   std_logic_vector(1 downto 0);
      slavebuserrint   : out   std_logic;

      masterhclk       : in    std_logic                                := '0';
      masterhgrant     : in    std_logic                                := '0';
      masterhready     : in    std_logic                                := '0';
      masterhrdata     : in    std_logic_vector(31 downto 0)            := (others => '0');
      masterhresp      : in    std_logic_vector(1 downto 0)             := (others => '0');
      masterhwrite     : out   std_logic;
      masterhlock      : out   std_logic;
      masterhbusreq    : out   std_logic;
      masterhaddr      : out   std_logic_vector(31 downto 0);
      masterhburst     : out   std_logic_vector(2 downto 0);
      masterhsize      : out   std_logic_vector(1 downto 0);
      masterhtrans     : out   std_logic_vector(1 downto 0);
      masterhwdata     : out   std_logic_vector(31 downto 0);

      lockreqdp0       : in    std_logic                                := '0';
      lockreqdp1       : in    std_logic                                := '0';
      lockgrantdp0     : out   std_logic;
      lockgrantdp1     : out   std_logic;

      ebiack           : in    std_logic                                := '0';
      ebiclk           : out   std_logic                                := '0';
      ebiwen           : out   std_logic                                := '0';
      ebiaddr          : out   std_logic_vector(24 downto 0);
      ebibe            : out   std_logic_vector(1 downto 0);
      ebicsn           : out   std_logic_vector(3 downto 0);
      ebioen           : out   std_logic                                := '0';
      ebidq            : inout std_logic_vector(15 downto 0)            := (others => '0');

      uartctsn         : in    std_logic                                := '0';
      uartdsrn         : in    std_logic                                := '0';
      uartrxd          : in    std_logic                                := '0';
      uarttxd          : out   std_logic                                := '0';
      uartrtsn         : out   std_logic                                := '0';
      uartrin          : inout std_logic                                := '0';
      uartdcdn         : inout std_logic                                := '0';
      uartdtrn         : out   std_logic                                := '0';

      sdramclk         : out   std_logic                                := '0';
      sdramaddr        : out   std_logic_vector(14 downto 0);
      sdramcsn         : out   std_logic_vector(1 downto 0);
      sdramdq          : inout std_logic_vector(sdram_width-1 downto 0) := (others => '0');
      sdramdqm         : out   std_logic_vector(sdramdqm_width-1 downto 0);
      sdramdqs         : inout std_logic_vector(sdramdqm_width-1 downto 0) := (others => '0');
      sdramclke        : out   std_logic                                := '0';
      sdramclkn        : out   std_logic                                := '0';
      sdramwen         : out   std_logic                                := '0';
      sdramcasn        : out   std_logic                                := '0';
      sdramrasn        : out   std_logic                                := '0';

      intextpin        : in    std_logic                                := '0';
      traceclk         : out   std_logic                                := '0';
      tracesync        : out   std_logic                                := '0';
      tracepipestat    : out   std_logic_vector(2 downto 0);
      tracepkt         : out   std_logic_vector(15 downto 0);

      dp0_2_portaclk   : in    std_logic                                := '0';
      dp0_portaena     : in    std_logic                                := '0';
      dp0_portawe      : in    std_logic                                := '0';
      dp0_portaaddr    : in    std_logic_vector(dp0_widthad-1 downto 0) := (others => '0');
      dp0_portadatain  : in    std_logic_vector(dp0_width-1 downto 0)   := (others => '0');
      dp0_portadataout : out   std_logic_vector(dp0_width-1 downto 0);
      dp0_portbclk     : in    std_logic                                := '0';
      dp0_portbena     : in    std_logic                                := '0';
      dp0_portbwe      : in    std_logic                                := '0';
      dp0_portbaddr    : in    std_logic_vector(dp0_widthad-1 downto 0) := (others => '0');
      dp0_portbdatain  : in    std_logic_vector(dp0_width-1 downto 0)   := (others => '0');
      dp0_portbdataout : out   std_logic_vector(dp0_width-1 downto 0);

      dp1_3_portaclk   : in    std_logic                                := '0';
      dp1_portaena     : in    std_logic                                := '0';
      dp1_portawe      : in    std_logic                                := '0';
      dp1_portaaddr    : in    std_logic_vector(dp1_widthad-1 downto 0) := (others => '0');
      dp1_portadatain  : in    std_logic_vector(dp1_width-1 downto 0)   := (others => '0');
      dp1_portadataout : out   std_logic_vector(dp1_width-1 downto 0);
      dp1_portbclk     : in    std_logic                                := '0';
      dp1_portbena     : in    std_logic                                := '0';
      dp1_portbwe      : in    std_logic                                := '0';
      dp1_portbaddr    : in    std_logic_vector(dp1_widthad-1 downto 0) := (others => '0');
      dp1_portbdatain  : in    std_logic_vector(dp1_width-1 downto 0)   := (others => '0');
      dp1_portbdataout : out   std_logic_vector(dp1_width-1 downto 0);

      dp2_portaena     : in    std_logic                                := '0';
      dp2_portawe      : in    std_logic                                := '0';
      dp2_portaaddr    : in    std_logic_vector(dp0_widthad-1 downto 0) := (others => '0');
      dp2_portadatain  : in    std_logic_vector(dp0_width-1 downto 0)   := (others => '0');
      dp2_portadataout : out   std_logic_vector(dp0_width-1 downto 0);

      dp3_portaena     : in    std_logic                                := '0';
      dp3_portawe      : in    std_logic                                := '0';
      dp3_portaaddr    : in    std_logic_vector(dp1_widthad-1 downto 0) := (others => '0');
      dp3_portadatain  : in    std_logic_vector(dp1_width-1 downto 0)   := (others => '0');
      dp3_portadataout : out   std_logic_vector(dp1_width-1 downto 0);

      gpi           : in  std_logic_vector(gpio_width-1 downto 0) := (others => '0');
      gpo           : out std_logic_vector(gpio_width-1 downto 0));
end component;

component altddio_in
generic (
    width                  : positive; -- required parameter
    intended_device_family : string := "MERCURY";
    power_up_high          : string := "OFF";
    lpm_type               : string := "altddio_in"
);
port (
    datain    : in std_logic_vector(width-1 downto 0);
    inclock   : in std_logic;
    inclocken : in std_logic := '1';
    aset      : in std_logic := '0';
    aclr      : in std_logic := '0';

    dataout_h : out std_logic_vector(width-1 downto 0);
    dataout_l : out std_logic_vector(width-1 downto 0)
);
end component;

component altddio_out
generic (
    width                  : positive;  -- required parameter
    power_up_high          : string := "OFF";
    oe_reg                 : string := "UNUSED";
    extend_oe_disable      : string := "UNUSED";
    intended_device_family : string := "MERCURY";
    lpm_type               : string := "altddio_out"
    );
port (
    datain_h   : in std_logic_vector(width-1 downto 0);
    datain_l   : in std_logic_vector(width-1 downto 0);
    outclock   : in std_logic;
    outclocken : in std_logic := '1';
    aset       : in std_logic := '0';
    aclr       : in std_logic := '0';
    oe         : in std_logic := '1';

    dataout    : out std_logic_vector(width-1 downto 0)
);
end component;

component altddio_bidir
generic(
    width                    : positive; -- required parameter
    power_up_high            : string := "OFF";
    oe_reg                   : string := "UNUSED";
    extend_oe_disable        : string := "UNUSED";
    implement_input_in_lcell : string := "UNUSED";
    intended_device_family   : string := "MERCURY";
    lpm_type                 : string := "altddio_bidir"
);
port (
    datain_h   : in std_logic_vector(width-1 downto 0);
    datain_l   : in std_logic_vector(width-1 downto 0);
    inclock    : in std_logic;
    inclocken  : in std_logic := '1';
    outclock   : in std_logic;
    outclocken : in std_logic := '1';
    aset       : in std_logic := '0';
    aclr       : in std_logic := '0';
    oe         : in std_logic := '1';

    dataout_h  : out std_logic_vector(width-1 downto 0);