📄 stratix_components.vhd
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-- Copyright (C) 1988-2004 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
-- Quartus II 4.0 Build 190 1/28/2004
library IEEE, stratix;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use stratix.atom_pack.all;
package STRATIX_COMPONENTS is
--
-- STRATIX_LCELL
--
component stratix_lcell
generic
(
operation_mode : string := "normal";
synch_mode : string := "off";
register_cascade_mode : string := "off";
sum_lutc_input : string := "datac";
lut_mask : string := "ffff";
power_up : string := "low";
cin0_used : string := "false";
cin1_used : string := "false";
cin_used : string := "false";
output_mode : string := "comb_only";
lpm_type : string := "stratix_lcell";
x_on_violation : string := "on"
);
port
(
clk : in std_logic := '0';
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
cin : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '1';
inverta : in std_logic := '0';
regcascin : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
combout : out std_logic;
regout : out std_logic;
cout : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
end component;
--
-- STRATIX_IO
--
component stratix_io
generic
(
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_sync_reset : string := "none";
output_power_up : string := "low";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_sync_reset : string := "none";
oe_power_up : string := "low";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_sync_reset : string := "none";
input_power_up : string := "low";
extend_oe_disable : string := "false";
sim_dll_phase_shift : string := "0";
sim_dqs_input_frequency : string := "10000 ps";
lpm_type : string := "stratix_io"
);
port
(
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
delayctrlin : in std_logic := '0';
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsundelayedout : out std_logic;
padio : inout std_logic
);
end component;
--
-- STRATIX_MAC_MULT
--
component stratix_mac_mult
generic
(
dataa_width : integer := 0;
datab_width : integer := 0;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "stratix_mac_mult"
);
port
(
dataa : in std_logic_vector (17 downto 0) := (others => '0');
datab : in std_logic_vector (17 downto 0) := (others => '0');
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector (3 downto 0) := "0000";
aclr : in std_logic_vector (3 downto 0) := "0000";
ena : in std_logic_vector (3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector (35 downto 0);
scanouta : out std_logic_vector (17 downto 0);
scanoutb : out std_logic_vector (17 downto 0)
);
end component;
--
-- STRATIX_MAC_OUT
--
component stratix_mac_out
generic
(
operation_mode : string := "output_only";
dataa_width : integer := 0;
datab_width : integer := 0;
datac_width : integer := 0;
datad_width : integer := 0;
dataout_width : integer := 0;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
overflow_programmable_invert : std_logic := '0';
data_out_programmable_invert : std_logic_vector(71 downto 0)
:= (OTHERS => '0');
lpm_hint : string := "true";
lpm_type : string := "stratix_mac_out"
);
port
(
dataa : in std_logic_vector (35 downto 0) := (others => '0');
datab : in std_logic_vector (35 downto 0) := (others => '0');
datac : in std_logic_vector (35 downto 0) := (others => '0');
datad : in std_logic_vector (35 downto 0) := (others => '0');
zeroacc : in std_logic := '0';
addnsub0 : in std_logic := '1';
addnsub1 : in std_logic := '1';
signa : in std_logic := '1';
signb : in std_logic := '1';
clk : in std_logic_vector (3 downto 0) := "0000";
aclr : in std_logic_vector (3 downto 0) := "0000";
ena : in std_logic_vector (3 downto 0) := "1111";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic_vector (71 downto 0);
accoverflow : out std_logic
);
end component;
--
-- STRATIX_RAM_BLOCK
--
component stratix_ram_block
generic
(
operation_mode : string := "single_port";
mixed_port_feed_through_mode : string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name : string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout : string := "none";
data_interleave_width_in_bits : integer := 1;
data_interleave_offset_in_bits : integer := 1;
port_a_logical_ram_depth : integer := 0;
port_a_logical_ram_width : integer := 0;
port_a_data_in_clear : string := "none";
port_a_address_clear : string := "none";
port_a_write_enable_clear : string := "none";
port_a_data_out_clock : string := "none";
port_a_data_out_clear : string := "none";
port_a_first_address : integer := 0;
port_a_last_address : integer := 0;
port_a_first_bit_number : integer := 0;
port_a_data_width : integer := 144;
port_a_byte_enable_clear : string := "none";
port_a_data_in_clock : string := "clock0";
port_a_address_clock : string := "clock0";
port_a_write_enable_clock : string := "clock0";
port_a_byte_enable_clock : string := "clock0";
port_b_logical_ram_depth : integer := 0;
port_b_logical_ram_width : integer := 0;
port_b_data_in_clock : string := "none";
port_b_data_in_clear : string := "none";
port_b_address_clock : string := "none";
port_b_address_clear : string := "none";
port_b_read_enable_write_enable_clock : string := "none";
port_b_read_enable_write_enable_clear : string := "none";
port_b_data_out_clock : string := "none";
port_b_data_out_clear : string := "none";
port_b_first_address : integer := 0;
port_b_last_address : integer := 0;
port_b_first_bit_number : integer := 0;
port_b_data_width : integer := 144;
port_b_byte_enable_clear : string := "none";
port_b_byte_enable_clock : string := "none";
port_a_address_width : integer := 16;
port_b_address_width : integer := 16;
port_a_byte_enable_mask_width : integer := 0;
port_b_byte_enable_mask_width : integer := 0;
lpm_type : string := "stratix_ram_block";
connectivity_checking : string := "off";
mem1 : std_logic_vector(512 downto 1) := (OTHERS => '0');
mem2 : std_logic_vector(512 downto 1) := (OTHERS => '0');
mem3 : std_logic_vector(512 downto 1) := (OTHERS => '0');
mem4 : std_logic_vector(512 downto 1) := (OTHERS => '0');
mem5 : std_logic_vector(512 downto 1) := (OTHERS => '0');
mem6 : std_logic_vector(512 downto 1) := (OTHERS => '0');
mem7 : std_logic_vector(512 downto 1) := (OTHERS => '0');
mem8 : std_logic_vector(512 downto 1) := (OTHERS => '0');
mem9 : std_logic_vector(512 downto 1) := (OTHERS => '0')
);
port
(
portawe : in std_logic := '0';
portabyteenamasks : in std_logic_vector (15 downto 0) := (others => '1');
portbbyteenamasks : in std_logic_vector (15 downto 0) := (others => '1');
portbrewe : in std_logic := '0';
clr0 : in std_logic := '0';
clr1 : in std_logic := '0';
clk0 : in std_logic := '0';
clk1 : in std_logic := '0';
ena0 : in std_logic := '1';
ena1 : in std_logic := '1';
portadatain : in std_logic_vector (143 downto 0) := (others => '0');
portbdatain : in std_logic_vector (143 downto 0) := (others => '0');
portaaddr : in std_logic_vector (15 downto 0) := (others => '0');
portbaddr : in std_logic_vector (15 downto 0) := (others => '0');
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
portadataout : out std_logic_vector (143 downto 0);
portbdataout : out std_logic_vector (143 downto 0)
);
end component;
--
-- STRATIX_LVDS_TRANSMITTER
--
component stratix_lvds_transmitter
generic (
channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
lpm_type : string := "stratix_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge: VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge: VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01));
port (
clk0 : in std_logic;
enable0 : in std_logic;
datain : in std_logic_vector(9 downto 0);
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic);
end component;
--
-- STRATIX_LVDS_RECEIVER
--
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