pll_ram.tan.summary

来自「一本老师推荐的经典的VHDL覆盖基础的入门书籍」· SUMMARY 代码 · 共 42 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.369 ns
From           : wr_en
To             : lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.732 ns
From           : lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]
To             : package_full

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.133 ns
From           : rst
To             : dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[1]

Type           : Worst-case minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 2.399 ns
From           : pllx2:pllx2_u1|altpll:altpll_component|_clk0
To             : clk_out

Type           : Clock Setup: 'pllx2:pllx2_u1|altpll:altpll_component|_clk0'
Slack          : 6.087 ns
Required Time  : 100.00 MHz ( period = 10.000 ns )
Actual Time    : 255.56 MHz ( period = 3.913 ns )
From           : dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0
To             : dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0

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