pll_ram.eda.qmsg

一本老师推荐的经典的VHDL覆盖基础的入门书籍

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer " "Info: Running Quartus II EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 05 05:43:09 2004 " "Info: Processing started: Sun Dec 05 05:43:09 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --import_settings_files=off --export_settings_files=off pll_ram -c pll_ram " "Info: Command: quartus_eda --import_settings_files=off --export_settings_files=off pll_ram -c pll_ram" {  } {  } 0}
{ "Info" "IBASEO_DONE_HDL_SDO_GENERATION" "pll_ram.vo pll_ram_v.sdo d:/prj_d/modelsim_demo/pll_ram/simulation/modelsim/ simulation " "Info: Generated files pll_ram.vo and pll_ram_v.sdo in directory d:/prj_d/modelsim_demo/pll_ram/simulation/modelsim/ for EDA simulation tool" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s " "Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 05 05:43:10 2004 " "Info: Processing ended: Sun Dec 05 05:43:10 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}