pll_ram.map.qmsg

一本老师推荐的经典的VHDL覆盖基础的入门书籍

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 190 1/28/2004 SJ Full Version " "Info: Version 4.0 Build 190 1/28/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 05 05:42:18 2004 " "Info: Processing started: Sun Dec 05 05:42:18 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off pll_ram -c pll_ram " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off pll_ram -c pll_ram" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pllx2.v 1 1 " "Info: Found 1 design units and 1 entities in source file pllx2.v" { { "Info" "ISGN_ENTITY_NAME" "1 pllx2 " "Info: Found entity 1: pllx2" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pllx2.v" "pllx2" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pllx2.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll_ram.v 1 1 " "Info: Found 1 design units and 1 entities in source file pll_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 pll_ram " "Info: Found entity 1: pll_ram" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "pll_ram" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dpram8x32.v 1 1 " "Info: Found 1 design units and 1 entities in source file dpram8x32.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpram8x32 " "Info: Found entity 1: dpram8x32" {  } { { "d:/prj_d/modelsim_demo/pll_ram/dpram8x32.v" "dpram8x32" "" { Text "d:/prj_d/modelsim_demo/pll_ram/dpram8x32.v" 42 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 5 pll_ram.v(41) " "Warning: Verilog HDL expression warning at pll_ram.v(41): truncated operand with size 6 to match size of smaller operand (5)" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 41 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 pll_ram.v(59) " "Warning: Verilog HDL expression warning at pll_ram.v(59): truncated operand with size 2 to match size of smaller operand (1)" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 59 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/eda/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "altpll" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 325 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/eda/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "c:/eda/quartus/libraries/megafunctions/altsyncram.tdf" "altsyncram" "" { Text "c:/eda/quartus/libraries/megafunctions/altsyncram.tdf" 430 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_7bc1.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file db/altsyncram_7bc1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_7bc1 " "Info: Found entity 1: altsyncram_7bc1" {  } { { "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" "altsyncram_7bc1" "" { Text "d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf" 31 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "wr_addr\[0\]~5 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: wr_addr\[0\]~5" {  } { { "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" "" "wr_addr\[0\]~5" { Text "d:/prj_d/modelsim_demo/pll_ram/pll_ram.v" 38 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf" "lpm_counter" "" { Text "c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf" 221 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_stratix " "Info: Found entity 1: alt_counter_stratix" {  } { { "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" "alt_counter_stratix" "" { Text "c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf" 282 1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pllx2:pllx2_u1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL pllx2:pllx2_u1\|altpll:altpll_component\|pll feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance." {  } { { "c:/eda/quartus/libraries/megafunctions/altpll.tdf" "" "" { Text "c:/eda/quartus/libraries/megafunctions/altpll.tdf" 652 3 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "44 " "Info: Implemented 44 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "17 " "Info: Implemented 17 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "7 " "Info: Implemented 7 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "8 " "Info: Implemented 8 RAM segments" {  } {  } 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 3 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 05 05:42:22 2004 " "Info: Processing ended: Sun Dec 05 05:42:22 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}