pll_ram_hier_info

一本老师推荐的经典的VHDL覆盖基础的入门书籍

|pll_ram
clk_in => clk_in~0.IN1
rst => wr_addr[3].ACLR
rst => wr_addr[2].ACLR
rst => wr_addr[1].ACLR
rst => wr_addr[0].ACLR
rst => wr_addr[4].ACLR
data_in[0] => data_in[0]~7.IN1
data_in[1] => data_in[1]~6.IN1
data_in[2] => data_in[2]~5.IN1
data_in[3] => data_in[3]~4.IN1
data_in[4] => data_in[4]~3.IN1
data_in[5] => data_in[5]~2.IN1
data_in[6] => data_in[6]~1.IN1
data_in[7] => data_in[7]~0.IN1
wr_en => wr_en~0.IN1
rd_en => rd_en~0.IN1
rd_addr[0] => rd_addr[0]~4.IN1
rd_addr[1] => rd_addr[1]~3.IN1
rd_addr[2] => rd_addr[2]~2.IN1
rd_addr[3] => rd_addr[3]~1.IN1
rd_addr[4] => rd_addr[4]~0.IN1
clk_out <= clk.DB_MAX_OUTPUT_PORT_TYPE
lock <= pllx2:pllx2_u1.locked
package_full <= i~1.DB_MAX_OUTPUT_PORT_TYPE
data_out[0] <= dpram8x32:dpram8x32_u1.q
data_out[1] <= dpram8x32:dpram8x32_u1.q
data_out[2] <= dpram8x32:dpram8x32_u1.q
data_out[3] <= dpram8x32:dpram8x32_u1.q
data_out[4] <= dpram8x32:dpram8x32_u1.q
data_out[5] <= dpram8x32:dpram8x32_u1.q
data_out[6] <= dpram8x32:dpram8x32_u1.q
data_out[7] <= dpram8x32:dpram8x32_u1.q


|pll_ram|pllx2:pllx2_u1
inclk0 => sub_wire7[0].IN1
areset => areset~0.IN1
c0 <= altpll:altpll_component.clk
locked <= altpll:altpll_component.locked


|pll_ram|pllx2:pllx2_u1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
areset => pll.ARESET
clkena[0] => pll.ENA
clkena[1] => pll.ENA1
clkena[2] => pll.ENA2
clkena[3] => pll.ENA3
clkena[4] => pll.ENA4
clkena[5] => pll.ENA5
extclkena[0] => pll.EXTCLKENA
extclkena[1] => pll.EXTCLKENA1
extclkena[2] => pll.EXTCLKENA2
extclkena[3] => pll.EXTCLKENA3
clk[0] <= pll.CLK
clk[1] <= pll.CLK1
clk[2] <= pll.CLK2
clk[3] <= pll.CLK3
clk[4] <= pll.CLK4
clk[5] <= pll.CLK5
extclk[0] <= <UNC>
extclk[1] <= <UNC>
extclk[2] <= <UNC>
extclk[3] <= <UNC>
clkbad[0] <= <UNC>
clkbad[1] <= <UNC>
enable1 <= <UNC>
enable0 <= <UNC>
activeclock <= <UNC>
clkloss <= <UNC>
locked <= pll.LOCKED
scandataout <= <UNC>
scandone <= <UNC>
sclkout0 <= <UNC>
sclkout1 <= <UNC>


|pll_ram|dpram8x32:dpram8x32_u1
data[0] => data[0]~7.IN1
data[1] => data[1]~6.IN1
data[2] => data[2]~5.IN1
data[3] => data[3]~4.IN1
data[4] => data[4]~3.IN1
data[5] => data[5]~2.IN1
data[6] => data[6]~1.IN1
data[7] => data[7]~0.IN1
wren => wren~0.IN1
wraddress[0] => wraddress[0]~4.IN1
wraddress[1] => wraddress[1]~3.IN1
wraddress[2] => wraddress[2]~2.IN1
wraddress[3] => wraddress[3]~1.IN1
wraddress[4] => wraddress[4]~0.IN1
rdaddress[0] => rdaddress[0]~4.IN1
rdaddress[1] => rdaddress[1]~3.IN1
rdaddress[2] => rdaddress[2]~2.IN1
rdaddress[3] => rdaddress[3]~1.IN1
rdaddress[4] => rdaddress[4]~0.IN1
rden => rden~0.IN1
clock => clock~0.IN1
aclr => aclr~0.IN1
q[0] <= altsyncram:altsyncram_component.q_b
q[1] <= altsyncram:altsyncram_component.q_b
q[2] <= altsyncram:altsyncram_component.q_b
q[3] <= altsyncram:altsyncram_component.q_b
q[4] <= altsyncram:altsyncram_component.q_b
q[5] <= altsyncram:altsyncram_component.q_b
q[6] <= altsyncram:altsyncram_component.q_b
q[7] <= altsyncram:altsyncram_component.q_b


|pll_ram|dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component
wren_a => altsyncram_7bc1:auto_generated.wren_a
rden_b => altsyncram_7bc1:auto_generated.rden_b
data_a[0] => altsyncram_7bc1:auto_generated.data_a[0]
data_a[1] => altsyncram_7bc1:auto_generated.data_a[1]
data_a[2] => altsyncram_7bc1:auto_generated.data_a[2]
data_a[3] => altsyncram_7bc1:auto_generated.data_a[3]
data_a[4] => altsyncram_7bc1:auto_generated.data_a[4]
data_a[5] => altsyncram_7bc1:auto_generated.data_a[5]
data_a[6] => altsyncram_7bc1:auto_generated.data_a[6]
data_a[7] => altsyncram_7bc1:auto_generated.data_a[7]
address_a[0] => altsyncram_7bc1:auto_generated.address_a[0]
address_a[1] => altsyncram_7bc1:auto_generated.address_a[1]
address_a[2] => altsyncram_7bc1:auto_generated.address_a[2]
address_a[3] => altsyncram_7bc1:auto_generated.address_a[3]
address_a[4] => altsyncram_7bc1:auto_generated.address_a[4]
address_b[0] => altsyncram_7bc1:auto_generated.address_b[0]
address_b[1] => altsyncram_7bc1:auto_generated.address_b[1]
address_b[2] => altsyncram_7bc1:auto_generated.address_b[2]
address_b[3] => altsyncram_7bc1:auto_generated.address_b[3]
address_b[4] => altsyncram_7bc1:auto_generated.address_b[4]
clock0 => altsyncram_7bc1:auto_generated.clock0
aclr0 => altsyncram_7bc1:auto_generated.aclr0
q_a[0] <= <UNC>
q_a[1] <= <UNC>
q_a[2] <= <UNC>
q_a[3] <= <UNC>
q_a[4] <= <UNC>
q_a[5] <= <UNC>
q_a[6] <= <UNC>
q_a[7] <= <UNC>
q_b[0] <= altsyncram_7bc1:auto_generated.q_b[0]
q_b[1] <= altsyncram_7bc1:auto_generated.q_b[1]
q_b[2] <= altsyncram_7bc1:auto_generated.q_b[2]
q_b[3] <= altsyncram_7bc1:auto_generated.q_b[3]
q_b[4] <= altsyncram_7bc1:auto_generated.q_b[4]
q_b[5] <= altsyncram_7bc1:auto_generated.q_b[5]
q_b[6] <= altsyncram_7bc1:auto_generated.q_b[6]
q_b[7] <= altsyncram_7bc1:auto_generated.q_b[7]


|pll_ram|dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated
aclr0 => ram_block1a0.CLR0
aclr0 => ram_block1a1.CLR0
aclr0 => ram_block1a2.CLR0
aclr0 => ram_block1a3.CLR0
aclr0 => ram_block1a4.CLR0
aclr0 => ram_block1a5.CLR0
aclr0 => ram_block1a6.CLR0
aclr0 => ram_block1a7.CLR0
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_b[0] => ram_block1a0.PORTBADDR
address_b[0] => ram_block1a1.PORTBADDR
address_b[0] => ram_block1a2.PORTBADDR
address_b[0] => ram_block1a3.PORTBADDR
address_b[0] => ram_block1a4.PORTBADDR
address_b[0] => ram_block1a5.PORTBADDR
address_b[0] => ram_block1a6.PORTBADDR
address_b[0] => ram_block1a7.PORTBADDR
address_b[1] => ram_block1a0.PORTBADDR1
address_b[1] => ram_block1a1.PORTBADDR1
address_b[1] => ram_block1a2.PORTBADDR1
address_b[1] => ram_block1a3.PORTBADDR1
address_b[1] => ram_block1a4.PORTBADDR1
address_b[1] => ram_block1a5.PORTBADDR1
address_b[1] => ram_block1a6.PORTBADDR1
address_b[1] => ram_block1a7.PORTBADDR1
address_b[2] => ram_block1a0.PORTBADDR2
address_b[2] => ram_block1a1.PORTBADDR2
address_b[2] => ram_block1a2.PORTBADDR2
address_b[2] => ram_block1a3.PORTBADDR2
address_b[2] => ram_block1a4.PORTBADDR2
address_b[2] => ram_block1a5.PORTBADDR2
address_b[2] => ram_block1a6.PORTBADDR2
address_b[2] => ram_block1a7.PORTBADDR2
address_b[3] => ram_block1a0.PORTBADDR3
address_b[3] => ram_block1a1.PORTBADDR3
address_b[3] => ram_block1a2.PORTBADDR3
address_b[3] => ram_block1a3.PORTBADDR3
address_b[3] => ram_block1a4.PORTBADDR3
address_b[3] => ram_block1a5.PORTBADDR3
address_b[3] => ram_block1a6.PORTBADDR3
address_b[3] => ram_block1a7.PORTBADDR3
address_b[4] => ram_block1a0.PORTBADDR4
address_b[4] => ram_block1a1.PORTBADDR4
address_b[4] => ram_block1a2.PORTBADDR4
address_b[4] => ram_block1a3.PORTBADDR4
address_b[4] => ram_block1a4.PORTBADDR4
address_b[4] => ram_block1a5.PORTBADDR4
address_b[4] => ram_block1a6.PORTBADDR4
address_b[4] => ram_block1a7.PORTBADDR4
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
q_b[0] <= ram_block1a0.PORTBDATAOUT
q_b[1] <= ram_block1a1.PORTBDATAOUT
q_b[2] <= ram_block1a2.PORTBDATAOUT
q_b[3] <= ram_block1a3.PORTBDATAOUT
q_b[4] <= ram_block1a4.PORTBDATAOUT
q_b[5] <= ram_block1a5.PORTBDATAOUT
q_b[6] <= ram_block1a6.PORTBDATAOUT
q_b[7] <= ram_block1a7.PORTBDATAOUT
rden_b => ram_block1a0.PORTBRE
rden_b => ram_block1a1.PORTBRE
rden_b => ram_block1a2.PORTBRE
rden_b => ram_block1a3.PORTBRE
rden_b => ram_block1a4.PORTBRE
rden_b => ram_block1a5.PORTBRE
rden_b => ram_block1a6.PORTBRE
rden_b => ram_block1a7.PORTBRE
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE