📄 pll_ram.map.rpt
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node ; Logic Cells ; Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+-------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------------------+
; |pll_ram ; 7 (2) ; 5 ; 256 ; 0 ; 0 ; 0 ; 0 ; 28 ; 0 ; 2 (2) ; 0 (0) ; 5 (0) ; 5 (0) ; |pll_ram ;
; |dpram8x32:dpram8x32_u1| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pll_ram|dpram8x32:dpram8x32_u1 ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pll_ram|dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component ;
; |altsyncram_7bc1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pll_ram|dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated ;
; |lpm_counter:wr_addr_rtl_0| ; 5 (0) ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (0) ; 5 (0) ; |pll_ram|lpm_counter:wr_addr_rtl_0 ;
; |alt_counter_stratix:wysi_counter| ; 5 (5) ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 5 (5) ; 5 (5) ; |pll_ram|lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter ;
; |pllx2:pllx2_u1| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pll_ram|pllx2:pllx2_u1 ;
; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |pll_ram|pllx2:pllx2_u1|altpll:altpll_component ;
+-------------------------------------------+-------------+-----------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------------------------------------------------------------------------------------------+
+---------------------------------+
; Analysis & Synthesis Equations ;
+---------------------------------+
The equations can be found in d:/prj_d/modelsim_demo/pll_ram/pll_ram.map.eqn.
+-----------------------------------------------------------------------+
; Analysis & Synthesis Files Read ;
+------------------------------------------------------------------------
; File Name ; Read ;
+----------------------------------------------------------------+------+
; pllx2.v ; Read ;
; pll_ram.v ; Read ;
; dpram8x32.v ; Read ;
; c:/eda/quartus/libraries/megafunctions/altpll.tdf ; Read ;
; c:/eda/quartus/libraries/megafunctions/altsyncram.tdf ; Read ;
; d:/prj_d/modelsim_demo/pll_ram/db/altsyncram_7bc1.tdf ; Read ;
; c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf ; Read ;
; c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf ; Read ;
+----------------------------------------------------------------+------+
+------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-------------------------------------------------------------------------------
; Resource ; Usage ;
+-------------------------------+----------------------------------------------+
; Logic cells ; 7 ;
; Total combinational functions ; 7 ;
; Total registers ; 5 ;
; I/O pins ; 28 ;
; Total memory bits ; 256 ;
; Total PLLs ; 1 ;
; Maximum fan-out node ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ;
; Maximum fan-out ; 15 ;
; Total fan-out ; 163 ;
; Average fan-out ; 3.70 ;
+-------------------------------+----------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+--------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 32 ; 8 ; 32 ; 8 ; 256 ; None ;
+--------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+-----------------------------------------------------------------
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 5 ;
; Number of synthesis-generated cells ; 2 ;
; Number of WYSIWYG LUTs ; 5 ;
; Number of synthesis-generated LUTs ; 2 ;
; Number of WYSIWYG registers ; 5 ;
; Number of synthesis-generated registers ; 0 ;
; Number of cells with combinational logic only ; 2 ;
; Number of cells with registers only ; 0 ;
; Number of cells with combinational logic and registers ; 5 ;
+--------------------------------------------------------+-------+
+----------------------------------------------+
; General Register Statistics ;
+-----------------------------------------------
; Statistic ; Value ;
+--------------------------------------+-------+
; Number of registers using SCLR ; 0 ;
; Number of registers using SLOAD ; 0 ;
; Number of registers using ACLR ; 5 ;
; Number of registers using ALOAD ; 0 ;
; Number of registers using CLK_ENABLE ; 0 ;
; Number of registers using OE ; 0 ;
; Number of registers using PRESET ; 0 ;
+--------------------------------------+-------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Sun Dec 05 05:42:18 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off pll_ram -c pll_ram
Info: Found 1 design units and 1 entities in source file pllx2.v
Info: Found entity 1: pllx2
Info: Found 1 design units and 1 entities in source file pll_ram.v
Info: Found entity 1: pll_ram
Info: Found 1 design units and 1 entities in source file dpram8x32.v
Info: Found entity 1: dpram8x32
Warning: Verilog HDL expression warning at pll_ram.v(41): truncated operand with size 6 to match size of smaller operand (5)
Warning: Verilog HDL expression warning at pll_ram.v(59): truncated operand with size 2 to match size of smaller operand (1)
Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/altpll.tdf
Info: Found entity 1: altpll
Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Found 1 design units and 1 entities in source file db/altsyncram_7bc1.tdf
Info: Found entity 1: altsyncram_7bc1
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: wr_addr[0]~5
Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file c:/eda/quartus/libraries/megafunctions/alt_counter_stratix.tdf
Info: Found entity 1: alt_counter_stratix
Warning: Output port clk0 of PLL pllx2:pllx2_u1|altpll:altpll_component|pll feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance.
Info: Implemented 44 device resources after synthesis - the final resource count might be different
Info: Implemented 17 input pins
Info: Implemented 11 output pins
Info: Implemented 7 logic cells
Info: Implemented 8 RAM segments
Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
Info: Processing ended: Sun Dec 05 05:42:22 2004
Info: Elapsed time: 00:00:03
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