pll_ram.tan.rpt

一本老师推荐的经典的VHDL覆盖基础的入门书籍

; N/A   ; None         ; 3.320 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[7]                          ; clk_in   ;
; N/A   ; None         ; 3.320 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[6]                          ; clk_in   ;
; N/A   ; None         ; 3.320 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[5]                          ; clk_in   ;
; N/A   ; None         ; 3.320 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[4]                          ; clk_in   ;
; N/A   ; None         ; 3.320 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[3]                          ; clk_in   ;
; N/A   ; None         ; 3.320 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[2]                          ; clk_in   ;
; N/A   ; None         ; 3.320 ns   ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[1]                          ; clk_in   ;
+-------+--------------+------------+------------+-----------------------------------------------------------------------------------------------------------------------+----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; tco                                                                                                                                                          ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Required tco ; Actual tco ; From                                                                                         ; To           ; From Clock ;
+-------+--------------+------------+----------------------------------------------------------------------------------------------+--------------+------------+
; N/A   ; None         ; 5.732 ns   ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1]                         ; package_full ; clk_in     ;
; N/A   ; None         ; 5.360 ns   ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[4]                         ; package_full ; clk_in     ;
; N/A   ; None         ; 5.268 ns   ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[2]                         ; package_full ; clk_in     ;
; N/A   ; None         ; 5.125 ns   ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[3]                         ; package_full ; clk_in     ;
; N/A   ; None         ; 4.834 ns   ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]                         ; package_full ; clk_in     ;
; N/A   ; None         ; 4.538 ns   ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[2] ; data_out[2]  ; clk_in     ;
; N/A   ; None         ; 4.535 ns   ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[3] ; data_out[3]  ; clk_in     ;
; N/A   ; None         ; 4.533 ns   ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[4] ; data_out[4]  ; clk_in     ;
; N/A   ; None         ; 4.523 ns   ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[7] ; data_out[7]  ; clk_in     ;
; N/A   ; None         ; 4.510 ns   ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[1] ; data_out[1]  ; clk_in     ;
; N/A   ; None         ; 4.510 ns   ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[5] ; data_out[5]  ; clk_in     ;
; N/A   ; None         ; 4.499 ns   ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[6] ; data_out[6]  ; clk_in     ;
; N/A   ; None         ; 4.494 ns   ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] ; data_out[0]  ; clk_in     ;
; N/A   ; None         ; 2.399 ns   ; pllx2:pllx2_u1|altpll:altpll_component|_clk0                                                 ; clk_out      ; clk_in     ;
+-------+--------------+------------+----------------------------------------------------------------------------------------------+--------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                                                                      ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Minimum Slack ; Required th ; Actual th ; From       ; To                                                                                                                    ; To Clock ;
+---------------+-------------+-----------+------------+-----------------------------------------------------------------------------------------------------------------------+----------+
; N/A           ; None        ; -3.133 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0]                          ; clk_in   ;
; N/A           ; None        ; -3.133 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[7]                          ; clk_in   ;
; N/A           ; None        ; -3.133 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[6]                          ; clk_in   ;
; N/A           ; None        ; -3.133 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[5]                          ; clk_in   ;
; N/A           ; None        ; -3.133 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[4]                          ; clk_in   ;
; N/A           ; None        ; -3.133 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[3]                          ; clk_in   ;
; N/A           ; None        ; -3.133 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[2]                          ; clk_in   ;
; N/A           ; None        ; -3.133 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[1]                          ; clk_in   ;
; N/A           ; None        ; -3.148 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_we_reg       ; clk_in   ;
; N/A           ; None        ; -3.200 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_re_reg       ; clk_in   ;
; N/A           ; None        ; -3.230 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg0 ; clk_in   ;
; N/A           ; None        ; -3.230 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg1 ; clk_in   ;
; N/A           ; None        ; -3.230 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg2 ; clk_in   ;
; N/A           ; None        ; -3.230 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg3 ; clk_in   ;
; N/A           ; None        ; -3.230 ns ; rst        ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_