📄 pll_ram.tan.rpt
字号:
; Cut off feedback from I/O pins ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Number of paths to report ; 200 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type ; Slack ; Required Time ; Actual Time ; From ; To ;
+-------------------------------------------------------------+----------+-----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+
; Worst-case tsu ; N/A ; None ; 6.369 ns ; wr_en ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] ;
; Worst-case tco ; N/A ; None ; 5.732 ns ; lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[1] ; package_full ;
; Worst-case th ; N/A ; None ; -3.133 ns ; rst ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[1] ;
; Worst-case minimum tco ; N/A ; None ; 2.399 ns ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; clk_out ;
; Clock Setup: 'pllx2:pllx2_u1|altpll:altpll_component|_clk0' ; 6.087 ns ; 100.00 MHz ( period = 10.000 ns ) ; 255.56 MHz ( period = 3.913 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 ;
+-------------------------------------------------------------+----------+-----------------------------------+----------------------------------+----------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+----------------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+
; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; ; PLL output ; 100.0 MHz ; clk_in ; 2 ; 1 ; -2.176 ns ;
; clk_in ; ; User Pin ; 50.0 MHz ; NONE ; N/A ; N/A ; N/A ;
+----------------------------------------------+--------------------+------------+------------------+----------+-----------------------+---------------------+-----------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pllx2:pllx2_u1|altpll:altpll_component|_clk0' ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+----------+-----------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+----------------------------------------------+----------------------------------------------+-----------------------------+---------------------------+-------------------------+
; 6.087 ns ; 255.56 MHz ( period = 3.913 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg0 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.371 ns ; 3.284 ns ;
; 6.087 ns ; 255.56 MHz ( period = 3.913 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg1 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg1 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.371 ns ; 3.284 ns ;
; 6.087 ns ; 255.56 MHz ( period = 3.913 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg2 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg2 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.371 ns ; 3.284 ns ;
; 6.087 ns ; 255.56 MHz ( period = 3.913 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg3 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg3 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.371 ns ; 3.284 ns ;
; 6.087 ns ; 255.56 MHz ( period = 3.913 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg4 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg4 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.371 ns ; 3.284 ns ;
; 6.087 ns ; 255.56 MHz ( period = 3.913 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg5 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg5 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.371 ns ; 3.284 ns ;
; 6.087 ns ; 255.56 MHz ( period = 3.913 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg6 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg6 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.371 ns ; 3.284 ns ;
; 6.087 ns ; 255.56 MHz ( period = 3.913 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_datain_reg7 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~porta_memory_reg7 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.371 ns ; 3.284 ns ;
; 6.088 ns ; 255.62 MHz ( period = 3.912 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg4 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.372 ns ; 3.284 ns ;
; 6.088 ns ; 255.62 MHz ( period = 3.912 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg3 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.372 ns ; 3.284 ns ;
; 6.088 ns ; 255.62 MHz ( period = 3.912 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg2 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.372 ns ; 3.284 ns ;
; 6.088 ns ; 255.62 MHz ( period = 3.912 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg1 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.372 ns ; 3.284 ns ;
; 6.088 ns ; 255.62 MHz ( period = 3.912 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg0 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[0] ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.372 ns ; 3.284 ns ;
; 6.088 ns ; 255.62 MHz ( period = 3.912 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg4 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[7] ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.372 ns ; 3.284 ns ;
; 6.088 ns ; 255.62 MHz ( period = 3.912 ns ) ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|ram_block1a0~portb_address_reg3 ; dpram8x32:dpram8x32_u1|altsyncram:altsyncram_component|altsyncram_7bc1:auto_generated|q_b[7] ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; pllx2:pllx2_u1|altpll:altpll_component|_clk0 ; 10.000 ns ; 9.372 ns ; 3.284 ns ;
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