pll_ram.fit.eqn

一本老师推荐的经典的VHDL覆盖基础的入门书籍

--H1_safe_q[0] is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0] at LC_X39_Y29_N5
--operation mode is arithmetic

H1_safe_q[0]_lut_out = wr_en $ H1_safe_q[0];
H1_safe_q[0] = DFFEA(H1_safe_q[0]_lut_out, GLOBAL(G1__clk0), GLOBAL(rst), , , , );

--H1L31 is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]~COUT0 at LC_X39_Y29_N5
--operation mode is arithmetic

H1L31_cout_0 = H1_safe_q[0];
H1L31 = CARRY(H1L31_cout_0);

--H1L41 is lpm_counter:wr_addr_rtl_0|alt_counter_stratix:wysi_counter|safe_q[0]~COUT1 at LC_X39_Y29_N5
--operation mode is arithmetic

H1L41_cout_1 = H1_safe_q[0];
H1L41 = CARRY(H1L41_cout_1);


--A1L22 is i~24 at LC_X39_Y29_N4
--operation mode is normal

A1L22 = !H1_safe_q[3] # !H1_safe_q[2] # !H1_safe_q[4] # !H1_safe_q[1];


--A1L12 is i~1 at LC_X39_Y29_N3
--operation mode is normal

A1L12 = A1L22 # !H1_safe_q[0];


--rst is rst at Pin_M24
--operation mode is input

rst = INPUT();


--clk_in is clk_in at Pin_B12
--operation mode is input

clk_in = INPUT();


--wr_en is wr_en at Pin_F19
--operation mode is input

wr_en = INPUT();


--rd_en is rd_en at Pin_B17
--operation mode is input

rd_en = INPUT();


--data_in[7] is data_in[7] at Pin_E17
--operation mode is input

data_in[7] = INPUT();


--rd_addr[0] is rd_addr[0] at Pin_C18
--operation mode is input

rd_addr[0] = INPUT();


--rd_addr[1] is rd_addr[1] at Pin_A17
--operation mode is input

rd_addr[1] = INPUT();


--rd_addr[2] is rd_addr[2] at Pin_D18
--operation mode is input

rd_addr[2] = INPUT();


--rd_addr[3] is rd_addr[3] at Pin_E18
--operation mode is input

rd_addr[3] = INPUT();


--rd_addr[4] is rd_addr[4] at Pin_G20
--operation mode is input

rd_addr[4] = INPUT();


--data_in[6] is data_in[6] at Pin_E16
--operation mode is input

data_in[6] = INPUT();


--data_in[5] is data_in[5] at Pin_G18
--operation mode is input

data_in[5] = INPUT();


--data_in[4] is data_in[4] at Pin_F17
--operation mode is input

data_in[4] = INPUT();


--data_in[3] is data_in[3] at Pin_H18
--operation mode is input

data_in[3] = INPUT();


--data_in[2] is data_in[2] at Pin_H16
--operation mode is input

data_in[2] = INPUT();


--data_in[1] is data_in[1] at Pin_D17
--operation mode is input

data_in[1] = INPUT();


--data_in[0] is data_in[0] at Pin_G17
--operation mode is input

data_in[0] = INPUT();


--clk_out is clk_out at Pin_P8
--operation mode is output

clk_out = OUTPUT(GLOBAL(G1__clk0));


--lock is lock at Pin_F14
--operation mode is output

lock = OUTPUT(G1__locked);


--package_full is package_full at Pin_E21
--operation mode is output

package_full = OUTPUT(!A1L12);


--data_out[7] is data_out[7] at Pin_C15
--operation mode is output

data_out[7] = OUTPUT(F1_q_b[7]);


--data_out[6] is data_out[6] at Pin_B18
--operation mode is output

data_out[6] = OUTPUT(F1_q_b[6]);


--data_out[5] is data_out[5] at Pin_G19
--operation mode is output

data_out[5] = OUTPUT(F1_q_b[5]);


--data_out[4] is data_out[4] at Pin_C17
--operation mode is output

data_out[4] = OUTPUT(F1_q_b[4]);


--data_out[3] is data_out[3] at Pin_D16
--operation mode is output

data_out[3] = OUTPUT(F1_q_b[3]);


--data_out[2] is data_out[2] at Pin_C16
--operation mode is output

data_out[2] = OUTPUT(F1_q_b[2]);


--data_out[1] is data_out[1] at Pin_A19
--operation mode is output

data_out[1] = OUTPUT(F1_q_b[1]);


--data_out[0] is data_out[0] at Pin_F15
--operation mode is output

data_out[0] = OUTPUT(F1_q_b[0]);



--~STRATIX_FITTER_CREATED_GND is ~STRATIX_FITTER_CREATED_GND at LC_X39_Y29_N2
--operation mode is normal

~STRATIX_FITTER_CREATED_GND = GND;