pll_ram.vo

来自「一本老师推荐的经典的VHDL覆盖基础的入门书籍」· VO 代码 · 共 1,693 行 · 第 1/5 页

	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rd_en~combout ),
	.regout(),
	.ddioregout(),
	.padio(rd_en),
	.dqsundelayedout());
// synopsys translate_off
defparam \rd_en~I .operation_mode = "input";
defparam \rd_en~I .ddio_mode = "none";
defparam \rd_en~I .input_register_mode = "none";
defparam \rd_en~I .output_register_mode = "none";
defparam \rd_en~I .oe_register_mode = "none";
defparam \rd_en~I .input_async_reset = "none";
defparam \rd_en~I .output_async_reset = "none";
defparam \rd_en~I .oe_async_reset = "none";
defparam \rd_en~I .input_sync_reset = "none";
defparam \rd_en~I .output_sync_reset = "none";
defparam \rd_en~I .oe_sync_reset = "none";
defparam \rd_en~I .input_power_up = "low";
defparam \rd_en~I .output_power_up = "low";
defparam \rd_en~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_G17
stratix_io \data_in[0]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_in[0]~combout ),
	.regout(),
	.ddioregout(),
	.padio(data_in[0]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_in[0]~I .operation_mode = "input";
defparam \data_in[0]~I .ddio_mode = "none";
defparam \data_in[0]~I .input_register_mode = "none";
defparam \data_in[0]~I .output_register_mode = "none";
defparam \data_in[0]~I .oe_register_mode = "none";
defparam \data_in[0]~I .input_async_reset = "none";
defparam \data_in[0]~I .output_async_reset = "none";
defparam \data_in[0]~I .oe_async_reset = "none";
defparam \data_in[0]~I .input_sync_reset = "none";
defparam \data_in[0]~I .output_sync_reset = "none";
defparam \data_in[0]~I .oe_sync_reset = "none";
defparam \data_in[0]~I .input_power_up = "low";
defparam \data_in[0]~I .output_power_up = "low";
defparam \data_in[0]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_C18
stratix_io \rd_addr[0]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rd_addr[0]~combout ),
	.regout(),
	.ddioregout(),
	.padio(rd_addr[0]),
	.dqsundelayedout());
// synopsys translate_off
defparam \rd_addr[0]~I .operation_mode = "input";
defparam \rd_addr[0]~I .ddio_mode = "none";
defparam \rd_addr[0]~I .input_register_mode = "none";
defparam \rd_addr[0]~I .output_register_mode = "none";
defparam \rd_addr[0]~I .oe_register_mode = "none";
defparam \rd_addr[0]~I .input_async_reset = "none";
defparam \rd_addr[0]~I .output_async_reset = "none";
defparam \rd_addr[0]~I .oe_async_reset = "none";
defparam \rd_addr[0]~I .input_sync_reset = "none";
defparam \rd_addr[0]~I .output_sync_reset = "none";
defparam \rd_addr[0]~I .oe_sync_reset = "none";
defparam \rd_addr[0]~I .input_power_up = "low";
defparam \rd_addr[0]~I .output_power_up = "low";
defparam \rd_addr[0]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_A17
stratix_io \rd_addr[1]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rd_addr[1]~combout ),
	.regout(),
	.ddioregout(),
	.padio(rd_addr[1]),
	.dqsundelayedout());
// synopsys translate_off
defparam \rd_addr[1]~I .operation_mode = "input";
defparam \rd_addr[1]~I .ddio_mode = "none";
defparam \rd_addr[1]~I .input_register_mode = "none";
defparam \rd_addr[1]~I .output_register_mode = "none";
defparam \rd_addr[1]~I .oe_register_mode = "none";
defparam \rd_addr[1]~I .input_async_reset = "none";
defparam \rd_addr[1]~I .output_async_reset = "none";
defparam \rd_addr[1]~I .oe_async_reset = "none";
defparam \rd_addr[1]~I .input_sync_reset = "none";
defparam \rd_addr[1]~I .output_sync_reset = "none";
defparam \rd_addr[1]~I .oe_sync_reset = "none";
defparam \rd_addr[1]~I .input_power_up = "low";
defparam \rd_addr[1]~I .output_power_up = "low";
defparam \rd_addr[1]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_D18
stratix_io \rd_addr[2]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rd_addr[2]~combout ),
	.regout(),
	.ddioregout(),
	.padio(rd_addr[2]),
	.dqsundelayedout());
// synopsys translate_off
defparam \rd_addr[2]~I .operation_mode = "input";
defparam \rd_addr[2]~I .ddio_mode = "none";
defparam \rd_addr[2]~I .input_register_mode = "none";
defparam \rd_addr[2]~I .output_register_mode = "none";
defparam \rd_addr[2]~I .oe_register_mode = "none";
defparam \rd_addr[2]~I .input_async_reset = "none";
defparam \rd_addr[2]~I .output_async_reset = "none";
defparam \rd_addr[2]~I .oe_async_reset = "none";
defparam \rd_addr[2]~I .input_sync_reset = "none";
defparam \rd_addr[2]~I .output_sync_reset = "none";
defparam \rd_addr[2]~I .oe_sync_reset = "none";
defparam \rd_addr[2]~I .input_power_up = "low";
defparam \rd_addr[2]~I .output_power_up = "low";
defparam \rd_addr[2]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_E18
stratix_io \rd_addr[3]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rd_addr[3]~combout ),
	.regout(),
	.ddioregout(),
	.padio(rd_addr[3]),
	.dqsundelayedout());
// synopsys translate_off
defparam \rd_addr[3]~I .operation_mode = "input";
defparam \rd_addr[3]~I .ddio_mode = "none";
defparam \rd_addr[3]~I .input_register_mode = "none";
defparam \rd_addr[3]~I .output_register_mode = "none";
defparam \rd_addr[3]~I .oe_register_mode = "none";
defparam \rd_addr[3]~I .input_async_reset = "none";
defparam \rd_addr[3]~I .output_async_reset = "none";
defparam \rd_addr[3]~I .oe_async_reset = "none";
defparam \rd_addr[3]~I .input_sync_reset = "none";
defparam \rd_addr[3]~I .output_sync_reset = "none";
defparam \rd_addr[3]~I .oe_sync_reset = "none";
defparam \rd_addr[3]~I .input_power_up = "low";
defparam \rd_addr[3]~I .output_power_up = "low";
defparam \rd_addr[3]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_G20
stratix_io \rd_addr[4]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\rd_addr[4]~combout ),
	.regout(),
	.ddioregout(),
	.padio(rd_addr[4]),
	.dqsundelayedout());
// synopsys translate_off
defparam \rd_addr[4]~I .operation_mode = "input";
defparam \rd_addr[4]~I .ddio_mode = "none";
defparam \rd_addr[4]~I .input_register_mode = "none";
defparam \rd_addr[4]~I .output_register_mode = "none";
defparam \rd_addr[4]~I .oe_register_mode = "none";
defparam \rd_addr[4]~I .input_async_reset = "none";
defparam \rd_addr[4]~I .output_async_reset = "none";
defparam \rd_addr[4]~I .oe_async_reset = "none";
defparam \rd_addr[4]~I .input_sync_reset = "none";
defparam \rd_addr[4]~I .output_sync_reset = "none";
defparam \rd_addr[4]~I .oe_sync_reset = "none";
defparam \rd_addr[4]~I .input_power_up = "low";
defparam \rd_addr[4]~I .output_power_up = "low";
defparam \rd_addr[4]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X39_Y29_N2
stratix_lcell \~STRATIX_FITTER_CREATED_GND~I (
// Equation(s):
// \~STRATIX_FITTER_CREATED_GND  = GND

	.clk(),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\~STRATIX_FITTER_CREATED_GND ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \~STRATIX_FITTER_CREATED_GND~I .operation_mode = "normal";
defparam \~STRATIX_FITTER_CREATED_GND~I .synch_mode = "off";
defparam \~STRATIX_FITTER_CREATED_GND~I .register_cascade_mode = "off";
defparam \~STRATIX_FITTER_CREATED_GND~I .sum_lutc_input = "datac";
defparam \~STRATIX_FITTER_CREATED_GND~I .lut_mask = "0000";
defparam \~STRATIX_FITTER_CREATED_GND~I .output_mode = "comb_only";
// synopsys translate_on

// atom is at Pin_D17
stratix_io \data_in[1]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_in[1]~combout ),
	.regout(),
	.ddioregout(),
	.padio(data_in[1]),
	.dqsundelayedout());
// synopsys translate_off
defparam \data_in[1]~I .operation_mode = "input";
defparam \data_in[1]~I .ddio_mode = "none";
defparam \data_in[1]~I .input_register_mode = "none";
defparam \data_in[1]~I .output_register_mode = "none";
defparam \data_in[1]~I .oe_register_mode = "none";
defparam \data_in[1]~I .input_async_reset = "none";
defparam \data_in[1]~I .output_async_reset = "none";
defparam \data_in[1]~I .oe_async_reset = "none";
defparam \data_in[1]~I .input_sync_reset = "none";
defparam \data_in[1]~I .output_sync_reset = "none";
defparam \data_in[1]~I .oe_sync_reset = "none";
defparam \data_in[1]~I .input_power_up = "low";
defparam \data_in[1]~I .output_power_up = "low";
defparam \data_in[1]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_H16
stratix_io \data_in[2]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),