_primary.vhd

来自「一本老师推荐的经典的VHDL覆盖基础的入门书籍」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity pllx2 is
    port(
        inclk0          : in     vl_logic;
        areset          : in     vl_logic;
        c0              : out    vl_logic;
        locked          : out    vl_logic
    );
end pllx2;