sfli2310.c

Fil2310.c De-interlace芯片源码

	gB_Fli2300ClkCtrl12Shadow = 0x1F;
	fli2300_Write08(CLK_CTRL_12, gB_Fli2300ClkCtrl12Shadow);
	// power down all plls
	fli2300_Write08(CLK_CTRL_2, 0x0B); //FE 
	fli2300_Write08(CLK_CTRL_5, 0x0B); //SDI
	fli2300_Write08(CLK_CTRL_8, 0x5B); //BE
	// Disable DAC
	fli2300_Write08(DAC_CTRL_1, 0x01); 

} // end - fli2300_SetDeepSleepMode


//#ifdef _FLI2300_REV_BC_
//*******************************************************************************
// FUNCTION:	void fli2300_UnmaskInterrupt(Fli2300InterruptNumbers_t B_interruptNumber, BYTE B_interruptEdge)
//							 
//
// USAGE:		Configures the FLI2300 based interrupts 
//
// DESCRIPTION:	
//
// INPUT:		BYTE : Interrupt number which is to be enabled
//				BYTE : Edge of the Interrupt 
//						0 - Rising edge Inetrrupt 
//						1 - Falling edge Inetrrupt
// OUTPUT:		None
//
// GLOBALS:		
//
// USED_REGS:	INT_MASK_L, INT_EDGE_L, 
//
//*******************************************************************************
void fli2300_UnmaskInterrupt(Fli2300InterruptNumbers_t B_interruptNumber, BYTE B_interruptEdge )
{
	gB_Fli2300IntMaskCtrlShadow |=  ((DWORD)0x01 << B_interruptNumber) ; 
	fli2300_Write24(INT_MASK_L, gB_Fli2300IntMaskCtrlShadow);

	gB_Fli2300IntEdgeCtrlShadow |= ((DWORD)B_interruptEdge << B_interruptNumber) ; 
	fli2300_Write24(INT_EDGE_L, gB_Fli2300IntEdgeCtrlShadow);
} // end - fli2300_UnmaskInterrupt

//*******************************************************************************
// FUNCTION:	void fli2300_MaskInterrupt(BYTE B_interruptNumber)
//
// USAGE:		Mask the specific interrupt 
//
// DESCRIPTION:	
//
// INPUT:		BYTE - Interrupt number which is to be masked 
//
// OUTPUT:		None
//
// GLOBALS:		gB_Fli2300IntMaskCtrlShadow
//
// USED_REGS: INT_MASK_L
//*******************************************************************************
void fli2300_MaskInterrupt(Fli2300InterruptNumbers_t B_interruptNumber)
{
	gB_Fli2300IntMaskCtrlShadow &=  ~((DWORD)0x000001 << B_interruptNumber) ; 
	fli2300_Write24(INT_MASK_L, gB_Fli2300IntMaskCtrlShadow);
}// end - fli2300_MaskInterrupt


//*******************************************************************************
// FUNCTION:	BYTE fli2300_GetInterruptStatus(Fli2300InterruptNumbers_t B_interruptNumber)
//
// USAGE:		Retunrs specified interrupt status 
//
// DESCRIPTION:	
//
// INPUT:		BYTE - Interrupt Number 
//
// OUTPUT:		BYTE - Interrupt status
//
// GLOBALS:		None
//
// USED_REGS:	INT_STATUS_L
//*******************************************************************************
BYTE fli2300_GetInterruptStatus(Fli2300InterruptNumbers_t B_interruptNumber)
{
	DWORD InterruptStatus ; 
	DWORD Temp ; 

	Temp = ( (DWORD)0x01 << B_interruptNumber ) ; 
	InterruptStatus = fli2300_Read16(INT_STATUS_L) ; 
	InterruptStatus |= ((DWORD)fli2300_Read08(INT_STATUS_L+2) << 16) ; 
 	if ( (InterruptStatus & Temp) == Temp)
	{
		fli2300_Write24(INT_STATUS_L,Temp) ; // clear the interrupt 
		return 1 ; 
	}
		return 0 ; 
}// end - fli2300_GetInterruptStatus

//clock.c
//*******************************************************************************
// FUNCTION:	void fli2300_EnableClock(BYTE SelectionFlag)
//
// USAGE:		This module enables the given clocks
//
// DESCRIPTION:	
//
// INPUT:		SelectionFlag - ORed value of Clocks selected
//								D_FLI2300_ALL_CLK	
//								D_FLI2300_FE_CLK	
//								D_FLI2300_SDI_CLK	
//								D_FLI2300_BE_CLK
//								D_FLI2300_VSC_CLK
//								D_FLI2300_AS_CLK
//
// OUTPUT:		None
//
// GLOBALS:
//
// USED_REGS:	CLK_CTRL_12
//*******************************************************************************
void fli2300_EnableClock(BYTE SelectionFlag)
{
	gB_Fli2300ClkCtrl12Shadow |= SelectionFlag;
	fli2300_Write08(CLK_CTRL_12, gB_Fli2300ClkCtrl12Shadow);
} // end - fli2300_EnableClock

//*******************************************************************************
// FUNCTION:	void fli2300_DisableClock(BYTE SelectionFlag)
//
// USAGE:		This module disables the given clocks
//
// DESCRIPTION:	
//
// INPUT:		SelectionFlag - ORed value of Clocks selected
//								D_FLI2300_ALL_CLK	
//								D_FLI2300_FE_CLK	
//								D_FLI2300_SDI_CLK	
//								D_FLI2300_BE_CLK
//								D_FLI2300_VSC_CLK
//								D_FLI2300_AS_CLK
//
// OUTPUT:		None
//
// GLOBALS:
//
// USED_REGS:	CLK_CTRL_12
//*******************************************************************************
void fli2300_DisableClock(BYTE SelectionFlag)
{
	gB_Fli2300ClkCtrl12Shadow &= ~(SelectionFlag);
	fli2300_Write08(CLK_CTRL_12, gB_Fli2300ClkCtrl12Shadow);
} // end - fli2300_DisableClock

//*******************************************************************************
// FUNCTION:	void fli2300_ConfigureClockReference(Fli2300ClockRefDesc_t *RefDesc)
//
// USAGE:		This module configures the clock refrence controls
//				The clock reference controls are as part of Clock reference Desc
//				Structure
//
// DESCRIPTION:	
//
// INPUT:		RefDesc	- pointer to Clock ref descriptor structure
//	
// OUTPUT:		None
//
// GLOBALS:
//
// USED_REGS:	CLK_CTRL_9, CLK_CTRL_10, CLK_CTRL_11
//*******************************************************************************
void fli2300_ConfigureClockReference(Fli2300ClockRefDesc_t *RefDesc)
{
	BYTE B_ClkRef;

	// Front clock reference and clock enable reference
	if (RefDesc->FEClockRef == Fli2300FEClockRef_ExtOscClk)
		B_ClkRef = 0x40;
	else
		B_ClkRef = (BYTE)RefDesc->FEClockRef;
	if (RefDesc->FEClockEnableRef == Fli2300FEClockRef_ExtOscClk)
		B_ClkRef = 0x80;
	else
		B_ClkRef = (BYTE) (RefDesc->FEClockRef << 3);
	fli2300_Write08(CLK_CTRL_9, B_ClkRef);

	// SDI and BE clock control
	gB_Fli2300ClkCtrl10Shadow = (BYTE) ((RefDesc->SDIClockRef) | (RefDesc->BEClockRef << 3)); 
	fli2300_Write08(CLK_CTRL_10, gB_Fli2300ClkCtrl10Shadow);

	//MC - ref clock, VSC clock referece, AS clock reference
	gB_Fli2300ClkCtrl11Shadow = (BYTE) ((RefDesc->VSClockRef) | (RefDesc->ASClockRef << 4));
	fli2300_Write08(CLK_CTRL_11, gB_Fli2300ClkCtrl11Shadow);

} // end - fli2300_ConfigureClockReference

//*******************************************************************************
// FUNCTION:	void fli2300_SetVSCClockReference(Fli2300VSClockRef_t Reference)
//
// USAGE:		This module sets the VSC clock refrence
//
// DESCRIPTION:	
//
// INPUT:		Reference	- VSC reference clock
//	
// OUTPUT:		None
//
// GLOBALS:
//
// USED_REGS:	CLK_CTRL_11
//*******************************************************************************
void fli2300_SetVSCClockReference(Fli2300VSClockRef_t Reference)
{
	gB_Fli2300ClkCtrl11Shadow &= 0xFC;
	gB_Fli2300ClkCtrl11Shadow |= (BYTE) Reference;
	fli2300_Write08(CLK_CTRL_11, gB_Fli2300ClkCtrl11Shadow);
} // end - fli2300_SetVSCClockReference

//*******************************************************************************
// FUNCTION:	extern void fli2300_SetBackEndPllReference(Fli2300BEClockRef_t Reference);
//
// USAGE:		This module sets the VSC clock refrence
//
// DESCRIPTION:	
//
// INPUT:		Reference	- VSC reference clock
//	
// OUTPUT:		None
//
// GLOBALS:
//
// USED_REGS:	CLK_CTRL_11
//*******************************************************************************
void fli2300_SetBackEndPllReference(Fli2300BEClockRef_t Reference)
{
	gB_Fli2300ClkCtrl10Shadow &= 0x07;
	gB_Fli2300ClkCtrl10Shadow |= (BYTE) (Reference << 3);
	fli2300_Write08(CLK_CTRL_10, gB_Fli2300ClkCtrl10Shadow);
} // end - fli2300_SetBackEndPllReference

//*******************************************************************************
// FUNCTION:	void fli2300_ConfigureFrontEndPll(Fli2300FEClkMode_t ClkMode,
//												  BYTE B_InputFreqMHz)
//
// USAGE:		This module programs the Front end clock pll settings and 
//				clock enable 1 and 2
//					1x mode - bypass pll
//					2x mode - mulitiply by 2
//					2x mode - mulitiply by 4
//
// DESCRIPTION:	
//
// INPUT:		ClkMode			- Multiplication factor
//				B_InputFreqMHz	- Input Frequency in MHz
//								(Input frequency rounded up to nearest integer)
//	
// OUTPUT:		None
//
// GLOBALS:
//
// USED_REGS:	CLK_CTRL_0, CLK_CTRL_1, CLK_CTRL_2, CLK_CTRL_2
//				FE_DIV_VALUE, FE_PLL_FEEDBACK_DIVIDER_L
//*******************************************************************************
//*******************************************************************************
// 2x and 4x Front end Pll divider settings
//*******************************************************************************

void fli2300_ConfigureFrontEndPll(Fli2300FEClkMode_t ClkMode, BYTE B_InputFreqMHz)
{
	BYTE B_TableIndex;

	fli2300_Write08(CLK_CTRL_0,0x00);	// disable clock doubler
	// bypass the front end pll - 1x clock
	if (ClkMode ==  Fli2300FEClkMode_x1)
	{
		fli2300_Write08(CLK_CTRL_2,0x19); //DEBUG
		// Clock enable 1 and 2 tied high
		fli2300_Write08(CLK_CTRL_3,0x00);
		return;
	}

	// 2x and 4x mode programming
	if (B_InputFreqMHz < 10) 
		return;
	if (B_InputFreqMHz < 16) 
		B_TableIndex = 0;
	else if (B_InputFreqMHz < 31) 
		B_TableIndex = 1;
	else if (B_InputFreqMHz < 61) 
		B_TableIndex = 2;
	else if (B_InputFreqMHz < 80) 
		B_TableIndex = 3;
	else
		return;

	fli2300_Write08(CLK_CTRL_3,0x01E);	// enable Clock enable 1 and 2
	fli2300_Write08(CLK_CTRL_2, 0x02);	// disable pll
	if (ClkMode ==  Fli2300FEClkMode_x2)
	{
		fli2300_Write08(CLK_CTRL_1, g_FEPll2xTable[B_TableIndex].MPDiv);
		fli2300_Write08(FE_DIV_VALUE, g_FEPll2xTable[B_TableIndex].ODiv);
		fli2300_Write16(FE_PLL_FEEDBACK_DIVIDER_L,g_FEPll2xTable[B_TableIndex].NDiv);
		fli2300_Write08(CLK_CTRL_2,g_FEPll2xTable[B_TableIndex].Ctrl);
	}
	else
	{
		fli2300_Write08(CLK_CTRL_1, g_FEPll4xTable[B_TableIndex].MPDiv);
		fli2300_Write08(FE_DIV_VALUE, g_FEPll4xTable[B_TableIndex].ODiv);
		fli2300_Write16(FE_PLL_FEEDBACK_DIVIDER_L,g_FEPll4xTable[B_TableIndex].NDiv);
		fli2300_Write08(CLK_CTRL_2,g_FEPll4xTable[B_TableIndex].Ctrl);
	}

} // end - fli2300_ConfigureFrontEndPll


//*******************************************************************************
// FUNCTION:	void fli2300_ConfigureSDRAMPll(BYTE B_InputFreqMHz)
//
// USAGE:		This module programs the SDRAM end clock pll settings 
//
// DESCRIPTION:	
//
// INPUT:		B_InputFreqMHz	- Input Frequency in MHz
//	
// OUTPUT:		None
//
// GLOBALS:		gSt_Fli2300PLLTable
//				gB_Fli2300PLLTableMinFreqMHz, gB_Fli2300PLLTableMaxFreqMHz
//
// USED_REGS:	CLK_CTRL_4, CLK_CTRL_5, SDI_DIV_VALUE,SDI_PLL_FEEDBACK_DIVIDER_L
//*******************************************************************************
void fli2300_ConfigureSDRAMPll(BYTE B_InputFreqMHz)
{
	BYTE B_RegValue;
	BYTE B_ClkCtrl;

	if (B_InputFreqMHz < gB_Fli2300PLLTableMinFreqMHz)
		return;
	if (B_InputFreqMHz > gB_Fli2300PLLTableMaxFreqMHz)
		return;
	
	B_InputFreqMHz = B_InputFreqMHz - gB_Fli2300PLLTableMinFreqMHz; //table index

	fli2300_Write08(CLK_CTRL_5,0x02); // disable pll
	
	B_RegValue = gSt_Fli2300PLLTable[B_InputFreqMHz].MDiv - 2;
	B_RegValue |= ((gSt_Fli2300PLLTable[B_InputFreqMHz].PDiv - 1) << 5);
	fli2300_Write08(CLK_CTRL_4,B_RegValue);
	fli2300_Write16(SDI_PLL_FEEDBACK_DIVIDER_L,(WORD)(gSt_Fli2300PLLTable[B_InputFreqMHz].NDiv - 2));

	B_ClkCtrl = 0x00;
	B_RegValue  = 0x00;
	if (gSt_Fli2300PLLTable[B_InputFreqMHz].ODiv == 1)
		B_ClkCtrl |= 0x08; // ODIV bypass when output divider = 1
	if (gSt_Fli2300PLLTable[B_InputFreqMHz].ODiv == 4)
		B_RegValue = 0x01;
	
	fli2300_Write08(SDI_DIV_VALUE, B_RegValue);
	fli2300_Write08(CLK_CTRL_5, B_ClkCtrl);

} // end - fli2300_ConfigureSDRAMPll


//*******************************************************************************
// FUNCTION:	void fli2300_ConfigureBackEndPllByTable(BYTE B_InputFreqMHz)
//
// USAGE:		This module programs the Back clock pll settings 
//				The Backend pll is used in case caded mode
//				This pll settings are taken from a pre generated table
//
// DESCRIPTION:	
//
// INPUT:		B_InputFreqMHz	- Input Frequency in MHz
//	
// OUTPUT:		None
//
// GLOBALS:		gSt_Fli2300BEPLLTable
//				gB_Fli2300BEPLLTableMinFreqMHz, gB_Fli2300BEPLLTableMaxFreqMHz
//
// USED_REGS:	CLK_CTRL_6, CLK_CTRL_7, CLK_CTRL_8
//				BE_PLL_FEEDBACK_DIVIDER_1_L, BE_PLL_FEEDBACK_DIVIDER_2_L	
//				BE_DIV_VALUE
//*******************************************************************************
void fli2300_ConfigureBackEndPllByTable(BYTE B_InputFreqMHz)
{
	BYTE B_RegValue;
	BYTE B_ClkCtrl;

	if (B_InputFreqMHz < gB_Fli2300BEPLLTableMinFreqMHz)
		return;
	if (B_InputFreqMHz > gB_Fli2300BEPLLTableMaxFreqMHz)
		return;
	
	B_InputFreqMHz = B_InputFreqMHz - gB_Fli2300BEPLLTableMinFreqMHz; //table index

	fli2300_Write08(CLK_CTRL_8,0x12); // disable pll

	B_RegValue = gSt_Fli2300BEPLLTable[B_InputFreqMHz].MDiv1 - 2;
	B_RegValue |= ((gSt_Fli2300BEPLLTable[B_InputFreqMHz].PDiv1 - 1) << 5);
	fli2300_Write08(CLK_CTRL_6, B_RegValue);
	fli2300_Write16(BE_PLL_FEEDBACK_DIVIDER_1_L, (WORD)(gSt_Fli2300BEPLLTable[B_InputFreqMHz].NDiv1 - 2));

  	B_RegValue = gSt_Fli2300BEPLLTable[B_InputFreqMHz].MDiv2 - 2;
	B_RegValue |= ((gSt_Fli2300BEPLLTable[B_InputFreqMHz].PDiv2 - 1) << 5);
	fli2300_Write08(CLK_CTRL_7, B_RegValue);
	fli2300_Write16(BE_PLL_FEEDBACK_DIVIDER_2_L, (WORD)(gSt_Fli2300BEPLLTable[B_InputFreqMHz].NDiv2 - 2));

	B_ClkCtrl = 0x00;
	B_RegValue  = 0x00;

	if (gSt_Fli2300BEPLLTable[B_InputFreqMHz].ODiv == 1)
		B_ClkCtrl |= 0x40; // ODIV bypass when output divider = 1