sad9882.c

Ad9882.c analog公司VGA/DVI AD芯片源码

/*------------------------------------------------------------------------
--  Copyright 2003 by Silicon Optix Inc.  All rights reserved. 
--
--  This document contains proprietary and confidential information of
--  Silicon Optix Inc. Distribution, copying, disclosure, or incorporation
--  in other material in whole, in part, or modified form is strictly 
--  prohibited without written permission from Silicon Optix Inc. 
--  Use of this information must be in accordance with the Silicon Optix
--  Software Licensing Agreement. If this information is received in error, 
--  please delete and notify us immediately.
--
------------------------------------------------------------------------
-- File Name  : sAd9882.c
-- Purpose    : 
--            :
------------------------------------------------------------------------
-- Revision History:
------------------------------------------------------------------------
-- <See $Log at end for detailed CVS history>
-- 
-- Creator's Name : Hung Nguyen
-- Creation Date  : Oct. 10, 2003
-- Comment        : 
--
-- Revision   : 
-- Name       : 
-- Date       :
-- Comment    :
--                                                                   
*-------------------------------------------------------------------------
$Id: sAd9882.c,v 1.2 2003/10/16 17:39:16 lawrence Exp $
*/

#define SAD9882_C
/****************************************************************************/
/*  I N C L U D E    F I L E S                                                       */
/****************************************************************************/

#include "main/aConfig.h"
#include "main/aGlobal.h"
#ifdef uI_NUCLEUS
#include	"nucleus.h"
#include	"Tc_defs.h"
#endif
#include "sd_defs.h"
#include "sd_extr.h"
#include "main/uItron/uI_types.h"
#include "main/uItron/uI_setm.h"
#include "main/uItron/uI_nplus.h"
#include "main/aInit.h"


#include "Driver.h"
#include "Driver/adc/dadc.h"
#include "Driver/adc/dadc2.h"
#include "Driver/common/aDrvTsk.h"
#include "Driver/Uart/dUart.h"
#include "Driver/Uart/dUart1.h"
#include "Driver/Uart/dUart2.h"
#include "aLogTsk.h"

#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "Image/Detect/sMode.h"
#include "Image/Detect/sPort.h"
#include "Image/Detect/sDetect.h"
#include "sAd9882.h"

extern BYTE by_qa_test_driver_enable;

#if ADC_OPTION ==ADC_9882 || ADC2_OPTION ==ADC_9882
BYTE byWriteSingleDataAd9882(BYTE by_reg_address, BYTE by_data)
{
	tst_ADC_WRITE_CONFIG st_adc_write_config;

#ifdef Use_DRV_NONBLOCKING_OPTION
	st_adc_write_config.t_blocking = BLOCKING;
#endif
	
	st_adc_write_config.t_change_priority = PRI_NO_CHANGE;
	st_adc_write_config.u32_delay = 0;
	st_adc_write_config.u32_max_count = 5;
	st_adc_write_config.u32_reg_address = by_reg_address;
	st_adc_write_config.u32_length = 1;
#if ADC_OPTION ==ADC_9882
	return st_adc_driver.Write(&by_data, &st_adc_write_config, &st_adc_driver);
#elif ADC2_OPTION ==ADC_9882
	return st_adc2_driver.Write(&by_data, &st_adc_write_config, &st_adc2_driver);
#endif
}

BYTE byReadSingleDataAd9882(BYTE by_reg_address, BYTE *byp_data)
{
	tst_ADC_READ_CONFIG st_adc_read_config;

#ifdef Use_DRV_NONBLOCKING_OPTION
	st_adc_read_config.t_blocking = BLOCKING;
#endif

	st_adc_read_config.t_change_priority = PRI_NO_CHANGE;
	st_adc_read_config.u32_delay = 0;
	st_adc_read_config.u32_max_count = 5;
	st_adc_read_config.u32_reg_address = by_reg_address;
	st_adc_read_config.u32_length = 1;
#if ADC_OPTION ==ADC_9882
	return st_adc_driver.Read(byp_data, &st_adc_read_config, &st_adc_driver);
#elif ADC2_OPTION ==ADC_9882
	return st_adc2_driver.Read(byp_data, &st_adc_read_config, &st_adc2_driver);
#endif
}

BYTE byAd9882InitMsr(UWORD32 u32_port_id)
{
	u32_ifm_msr_tmr[u32_port_id]=10;
	return OK;
}

BYTE byAd9882GetInitMsrDone(UWORD32 u32_port_id, UWORD32 *u32p_init_done)
{
	if(u32_ifm_msr_tmr[u32_port_id] == 0)
		*u32p_init_done = 1;
	else
		*u32p_init_done = 0;
	return OK;
}

BYTE byAd9882StartMsr(UWORD32 u32_port_id)
{
	u32_ifm_msr_tmr[u32_port_id] =10;
	return OK;
}

BYTE byAd9882GetMsrDone(UWORD32 u32_port_id, UWORD32 *u32p_msr_done)
{
	*u32p_msr_done = 1;
	return OK;
}

BYTE byAd9882GetMsrRaw(UWORD32 u32_port_id, st_RAW_MSR *stp_raw_msr )
{
	BYTE by_ret=0;
	return by_ret;
	
}

BYTE byAd9882SetInp(UWORD32 u32_port_id,BYTE by_input)     //PortSetInp
{
	BYTE by_ret=0;
	if(by_input == AD9882_DVI)
    {//Configure for DVI interface, using input vsync as Coast
		byWriteSingleDataAd9882(AD9882_ACTIVE_INTERFACE, 0x7E);
	}
	else
    {//Configure for Analog interface, using input vsync as Coast
		byWriteSingleDataAd9882(AD9882_ACTIVE_INTERFACE, 0x7C);
	}

	return by_ret;
}

BYTE byAd9882SetMode(UWORD32 u32_port_id, VP byptable)  //PortSetInpMode
{
	BYTE by_ret;
	BYTE *byp_table;

	byp_table = byptable;

	byWriteSingleDataAd9882(AD9882_CLAMP_COAST_CONTROL,0x00); //disable coast
	byWriteSingleDataAd9882(AD9882_STATE_CONTROL,0x02); //Full operation
	byWriteSingleDataAd9882(AD9882_STATE_CONTROL,0xE2);  //new for AD9882
	byWriteSingleDataAd9882(AD9882_VCO_CPMP, byp_table[0]); 
	byWriteSingleDataAd9882(AD9882_CLAMP_REPLACEMENT, 0x08);
	byWriteSingleDataAd9882(AD9882_CLAMP_DURATION, 0x14);
	byWriteSingleDataAd9882(AD9882_HSYNC_OUT_PULSEWIDTH, 0x20);
	byWriteSingleDataAd9882(AD9882_SYNC_SEPARATOR_THRESHOLD, 0x20);

	return by_ret;
}

BYTE byAd9882SetInpSetup(UWORD32 u32_port_id)  //PortSetInpSetup
{
	BYTE by_ret=0;
	BYTE by_temp;

	by_temp=0xC4; //  Init with Positive Hsync and Not invert Vsync
	if((sta_detect_info[u32_port_id].u32_inp_setup& BIT4)== BIT4)
	{//Negative hsync
		by_temp = by_temp & ~ BIT6; // Negative Hsync in
		by_temp = by_temp | BIT5; // Negative Hsync out
	}
	by_ret |= byWriteSingleDataAd9882(AD9882_SYNC_POLARITY_CONTROL, by_temp );
//	by_temp=0x24;
//	if((sta_detect_info[u32_port_id].u32_inp_setup& BIT4)== 0)		
//		by_temp = by_temp | BIT6;	/* HSPOL Hsync '+' polarity *///|BIT7
//	by_ret |= byWriteSingleDataAd9882(AD9882_SYNC_POLARITY_CONTROL, by_temp );
		
    by_temp=0x00;
	if((sta_detect_info[u32_port_id].u32_inp_setup & BIT5)== 0)			
		by_temp = by_temp | BIT1;	/* Coast '+' polarity */  //|BIT6
    by_ret |= byWriteSingleDataAd9882(AD9882_CLAMP_COAST_CONTROL, by_temp );
		
	return by_ret;
}
BYTE byAd9882SetRedOffset (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	by_ret |= byWriteSingleDataAd9882(AD9882_RED_OFFSET, (BYTE)(u32_value));
	return by_ret;
}

BYTE byAd9882SetBlueOffset (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	by_ret |= byWriteSingleDataAd9882(AD9882_BLUE_OFFSET, (BYTE)(u32_value));
	return by_ret;
}

BYTE byAd9882SetGreenOffset (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	by_ret |= byWriteSingleDataAd9882(AD9882_GREEN_OFFSET, (BYTE)(u32_value));
	return by_ret;
}

BYTE byAd9882SetRedGain (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	by_ret |= byWriteSingleDataAd9882(AD9882_RED_GAIN, (BYTE)(u32_value));
	return by_ret;
}

BYTE byAd9882SetBlueGain (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	by_ret |= byWriteSingleDataAd9882(AD9882_BLUE_GAIN, (BYTE)(u32_value));
	return by_ret;
}

BYTE byAd9882SetGreenGain (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	by_ret |= byWriteSingleDataAd9882(AD9882_GREEN_GAIN, (BYTE)(u32_value));
	return by_ret;
}

BYTE byAd9882SetBright (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	WORD w_data;
	struct st_EVENT_INFO st_event_info1;

	w_data = AD9882_BRIGHT_MAX - u32_value;
	w_data <<=1;
	by_ret |= byAd9882SetRedOffset(u32_port_id, (w_data));
	by_ret |= byAd9882SetBlueOffset(u32_port_id, (w_data));
	by_ret |= byAd9882SetGreenOffset(u32_port_id, (w_data));

	if (by_qa_test_driver_enable == 1)
	{
		st_event_info1.u16_severity=LOG;
		st_event_info1.u32_pc=0;
		strcpy(st_event_info1.bya_location,"byAd9882SetBright");
	
		byLogEvent(DEST_UART,0,&st_event_info1,"%d",u32_value);
	}

	return by_ret;
}

BYTE byAd9882SetContrast (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	struct st_EVENT_INFO st_event_info1;

	u32_value = AD9882_CONTRAST_MAX - u32_value;
	by_ret |= byAd9882SetRedGain(u32_port_id, (u32_value));
	by_ret |= byAd9882SetBlueGain(u32_port_id,(u32_value));
	by_ret |= byAd9882SetGreenGain(u32_port_id, (u32_value));

	if (by_qa_test_driver_enable == 1)
	{
		st_event_info1.u16_severity=LOG;
		st_event_info1.u32_pc=0;
		strcpy(st_event_info1.bya_location,"byAd9882SetContrast");
	
		byLogEvent(DEST_UART,0,&st_event_info1,"%d",u32_value);
	}

	return by_ret;
}

BYTE byAd9882SetRed (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	struct st_EVENT_INFO st_event_info1;

	by_ret |= byAd9882SetRedOffset(u32_port_id, (u32_value));
	by_ret |= byAd9882SetRedGain(u32_port_id,(u32_value));

	if (by_qa_test_driver_enable == 1)
	{
		st_event_info1.u16_severity=LOG;
		st_event_info1.u32_pc=0;
		strcpy(st_event_info1.bya_location,"byAd9882SetRed");
	
		byLogEvent(DEST_UART,0,&st_event_info1,"%d",u32_value);
	}

	return ERR;
}

BYTE byAd9882SetGreen (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	struct st_EVENT_INFO st_event_info1;

	by_ret |= byAd9882SetGreenOffset(u32_port_id, (u32_value));
	by_ret |= byAd9882SetGreenGain(u32_port_id,(u32_value));
	
	if (by_qa_test_driver_enable == 1)
	{
		st_event_info1.u16_severity=LOG;
		st_event_info1.u32_pc=0;
		strcpy(st_event_info1.bya_location,"byAd9882SetGreen");
	
		byLogEvent(DEST_UART,0,&st_event_info1,"%d",u32_value);
	}

	return ERR;
}

BYTE byAd9882SetBlue (UWORD32 u32_port_id, UWORD32 u32_value)
{
	BYTE by_ret=0;
	struct st_EVENT_INFO st_event_info1;

	by_ret |= byAd9882SetBlueOffset(u32_port_id, (u32_value));
	by_ret |= byAd9882SetBlueGain(u32_port_id,(u32_value));

	if (by_qa_test_driver_enable == 1)
	{
		st_event_info1.u16_severity=LOG;
		st_event_info1.u32_pc=0;
		strcpy(st_event_info1.bya_location,"byAd9882SetBlue");
	
		byLogEvent(DEST_UART,0,&st_event_info1,"%d",u32_value);
	}

	return ERR;
}

BYTE byAd9882SetClock (UWORD32 u32_port_id, UWORD32 u32_value) //PortSetInpMode
{
	BYTE by_ret=0;
	WORD w_data;
	struct st_EVENT_INFO st_event_info1;

	w_data = ((u32_value) - 1)<<4;

	by_ret |= byWriteSingleDataAd9882(AD9882_PLL_DIV_MSB, (BYTE)(w_data>>8));
	by_ret |= byWriteSingleDataAd9882(AD9882_PLL_DIV_LSB, (BYTE)(w_data));

	if (by_qa_test_driver_enable == 1)
	{
		st_event_info1.u16_severity=LOG;
		st_event_info1.u32_pc=0;
		strcpy(st_event_info1.bya_location,"byAd9882SetClock");
	
		byLogEvent(DEST_UART,0,&st_event_info1,"%d",u32_value);
	}

	return by_ret;
}

BYTE byAd9882SetPhase (UWORD32 u32_port_id, UWORD32 u32_value)  //PortSetInpMode
{
	BYTE by_ret=0;
	struct st_EVENT_INFO st_event_info1;

	by_ret |= byWriteSingleDataAd9882(AD9882_PHASE_ADJUST, (BYTE)(u32_value<<3));

	if (by_qa_test_driver_enable == 1)
	{
		st_event_info1.u16_severity=LOG;
		st_event_info1.u32_pc=0;
		strcpy(st_event_info1.bya_location,"byAd9882SetPhase");