counter2plus.vhd

来自「汽车四轮定位CCD驱动CPLD源代码」· VHDL 代码 · 共 50 行

library ieee;
use ieee.std_logic_1164.all;  --引用库
               
entity counter2plus is
    port(clk:in std_logic;    --输入：原始频率
         reset:in std_logic;  --复位
         RS: out std_logic;  --RS
         Gout:out std_logic); --输出：分频后输出
    signal tempGout : std_logic;--保存上次状态
    signal tempRS:    std_logic;--保存上次状态
end;
 
architecture behavioral of counter2plus is
signal countc: integer range 0 to 3;
begin
     process(reset,clk)

     begin
     if reset='1' then          --复位
        countc<=0;
        tempGout<='0';
        tempRS<='0';
     elsif clk'event and clk='1' then   --clk上升沿引发输出跳变
        countc<=countc+1;
        if countc>3 then
             countc<=0;
        end if;
        
        if countc=0 then
        	tempGout<='1';      --输出跳变  
        	tempRS<='0';
        elsif countc=1 then
            tempGout<='0';
            tempRS<='1';
        elsif countc=2 then
        	tempGout<='1';      --输出跳变  
        	tempRS<='0';
        elsif countc=3 then
            tempGout<='0';
            tempRS<='0';
        end if;

     end if;
     
     Gout<=tempGout;                 --输出
     RS<=tempRS;                     --输出
     
     end process;
end behavioral;