📄 tcd1208_driver.prd
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1| H0_countc_6|NOD| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| H0_countc_11|NOD| | A | 2 | 2 to [ 4]| 1 XOR free
5|H0_EfficiantDFFRH|NOD| | A | 2 | 2 to [ 5]| 1 XOR free
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8| H0_countc_7|NOD| | A | 2 | 2 to [ 8]| 1 XOR free
9| H0_countc_10|NOD| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| H0_countc_3|NOD| | A | 2 :+: 1| 2 to [12]| 1 XOR to [12]
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 4] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| H0_countc_2|NOD| | A | 3 |=> can support up to [ 10] logic PT(s)
1| H0_countc_6|NOD| | A | 1 |=> can support up to [ 13] logic PT(s)
2| | ? | | S | |=> can support up to [ 12] logic PT(s)
3| | ? | | S | |=> can support up to [ 10] logic PT(s)
4| H0_countc_11|NOD| | A | 2 |=> can support up to [ 13] logic PT(s)
5|H0_EfficiantDFFRH|NOD| | A | 2 |=> can support up to [ 13] logic PT(s)
6| | ? | | S | |=> can support up to [ 10] logic PT(s)
7| | ? | | S | |=> can support up to [ 12] logic PT(s)
8| H0_countc_7|NOD| | A | 2 |=> can support up to [ 15] logic PT(s)
9| H0_countc_10|NOD| | A | 1 |=> can support up to [ 13] logic PT(s)
10| | ? | | S | |=> can support up to [ 12] logic PT(s)
11| | ? | | S | |=> can support up to [ 15] logic PT(s)
12| H0_countc_3|NOD| | A | 2 :+: 1|=> can support up to [ 17] logic PT(s)
13| | ? | | S | |=> can support up to [ 15] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 4] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 4] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| H0_countc_2|NOD| | => | 5 6 7 0 | 48 49 50 43
1| H0_countc_6|NOD| | => | 5 6 7 0 | 48 49 50 43
2| | | | => | 6 7 0 1 | 49 50 43 44
3| | | | => | 6 7 0 1 | 49 50 43 44
4| H0_countc_11|NOD| | => | 7 0 1 2 | 50 43 44 45
5|H0_EfficiantDFFRH|NOD| | => | 7 0 1 2 | 50 43 44 45
6| | | | => | 0 1 2 3 | 43 44 45 46
7| | | | => | 0 1 2 3 | 43 44 45 46
8| H0_countc_7|NOD| | => | 1 2 3 4 | 44 45 46 47
9| H0_countc_10|NOD| | => | 1 2 3 4 | 44 45 46 47
10| | | | => | 2 3 4 5 | 45 46 47 48
11| | | | => | 2 3 4 5 | 45 46 47 48
12| H0_countc_3|NOD| | => | 3 4 5 6 | 46 47 48 49
13| | | | => | 3 4 5 6 | 46 47 48 49
14| | | | => | 4 5 6 7 | 47 48 49 50
15| | | | => | 4 5 6 7 | 47 48 49 50
---------------------------------------------------------------------------
===========================================================================
< Block [ 4] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 43| -| | ]
[RegIn 0 |198| -| | ]
[MCell 0 |197|NOD H0_countc_2| |*]
[MCell 1 |199|NOD H0_countc_6| |*]
1 [IOpin 1 | 44| -| | ]
[RegIn 1 |201| -| | ]
[MCell 2 |200| -| | ]
[MCell 3 |202| -| | ]
2 [IOpin 2 | 45| -| | ]
[RegIn 2 |204| -| | ]
[MCell 4 |203|NOD H0_countc_11| |*]
[MCell 5 |205|NOD H0_EfficiantDFFRH| |*]
3 [IOpin 3 | 46| -| | ]
[RegIn 3 |207| -| | ]
[MCell 6 |206| -| | ]
[MCell 7 |208| -| | ]
4 [IOpin 4 | 47| -| | ]
[RegIn 4 |210| -| | ]
[MCell 8 |209|NOD H0_countc_7| |*]
[MCell 9 |211|NOD H0_countc_10| |*]
5 [IOpin 5 | 48| -| | ]
[RegIn 5 |213| -| | ]
[MCell 10 |212| -| | ]
[MCell 11 |214| -| | ]
6 [IOpin 6 | 49| -| | ]
[RegIn 6 |216| -| | ]
[MCell 12 |215|NOD H0_countc_3| |*]
[MCell 13 |217| -| | ]
7 [IOpin 7 | 50| -| | ]
[RegIn 7 |219| -| | ]
[MCell 14 |218| -| | ]
[MCell 15 |220| -| | ]
---------------------------------------------------------------------------
===========================================================================
< Block [ 4] > Logic Array Fan-in
===========================================================================
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| Mcel 1 5 ( 133)| H0_countc_8
Mux01| Mcel 1 12 ( 143)| D0_GoutDFFRH
Mux02| IOPin 1 7 ( 5)| reset
Mux03| Mcel 4 5 ( 205)| H0_EfficiantDFFRH
Mux04| ... | ...
Mux05| Mcel 4 1 ( 199)| H0_countc_6
Mux06| Mcel 4 4 ( 203)| H0_countc_11
Mux07| Mcel 4 0 ( 197)| H0_countc_2
Mux08| Mcel 1 1 ( 127)| H0_countc_9
Mux09| Mcel 2 0 ( 149)| H0_countc_4
Mux10| Mcel 4 12 ( 215)| H0_countc_3
Mux11| ... | ...
Mux12| ... | ...
Mux13| ... | ...
Mux14| Mcel 4 9 ( 211)| H0_countc_10
Mux15| ... | ...
Mux16| Mcel 4 8 ( 209)| H0_countc_7
Mux17| Mcel 1 8 ( 137)| H0_countc_0
Mux18| ... | ...
Mux19| ... | ...
Mux20| ... | ...
Mux21| ... | ...
Mux22| ... | ...
Mux23| ... | ...
Mux24| ... | ...
Mux25| ... | ...
Mux26| Mcel 1 0 ( 125)| H0_countc_5
Mux27| Mcel 1 4 ( 131)| H0_countc_1
Mux28| ... | ...
Mux29| ... | ...
Mux30| ... | ...
Mux31| ... | ...
Mux32| ... | ...
---------------------------------------------------------------------------
===========================================================================
< Block [ 5] > Macrocell (MCell) Cluster Assignments
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
| Sync/Async-------+ | | | Cluster to Mcell Assignment
| Node Fixed(*)----+ | | | | | +- XOR PT Size
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| P0_countc_0|NOD| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
1| H0_jumpdown_3|NOD| | A | 2 | 2 to [ 1]| 1 XOR free
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| H0_jumpdown_8|NOD| | A | 2 | 2 to [ 4]| 1 XOR free
5| H0_jumpup_1|NOD| | A | 1 | 2 free | 1 XOR to [ 5] for 1 PT sig
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8| H0_jumpdown_7|NOD| | A | 2 | 2 to [ 8]| 1 XOR free
9| H0_jumpup_0|NOD| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| H0_jumpdown_4|NOD| | A | 2 | 2 to [12]| 1 XOR free
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 5] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| P0_countc_0|NOD| | S | 1 |=> can support up to [ 10] logic PT(s)
1| H0_jumpdown_3|NOD| | A | 2 |=> can support up to [ 17] logic PT(s)
2| | ? | | S | |=> can support up to [ 10] logic PT(s)
3| | ? | | S | |=> can support up to [ 12] logic PT(s)
4| H0_jumpdown_8|NOD| | A | 2 |=> can support up to [ 15] logic PT(s)
5| H0_jumpup_1|NOD| | A | 1 |=> can support up to [ 13] logic PT(s)
6| | ? | | S | |=> can support up to [ 12] logic PT(s)
7| | ? | | S | |=> can support up to [ 12] logic PT(s)
8| H0_jumpdown_7|NOD| | A | 2 |=> can support up to [ 15] logic PT(s)
9| H0_jumpup_0|NOD| | A | 1 |=> can support up to [ 13] logic PT(s)
10| | ? | | S | |=> can support up to [ 12] logic PT(s)
11| | ? | | S | |=> can support up to [ 15] logic PT(s)
12| H0_jumpdown_4|NOD| | A | 2 |=> can support up to [ 18] logic PT(s)
13| | ? | | S | |=> can support up to [ 15] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 5] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 5] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| P0_countc_0|NOD| | => | 5 6 7 0 | 57 56 55 62
1| H0_jumpdown_3|NOD| | => | 5 6 7 0 | 57 56 55 62
2| | | | => | 6 7 0 1 | 56 55 62 61
3| | | | => | 6 7 0 1 | 56 55 62 61
4| H0_jumpdown_8|NOD| | => | 7 0 1 2 | 55 62 61 60
5| H0_jumpup_1|NOD| | => | 7 0 1 2 | 55 62 61 60
6| | | | => | 0 1 2 3 | 62 61 60 59
7| | | | => | 0 1 2 3 | 62 61 60 59
8| H0_jumpdown_7|NOD| | => | 1 2 3 4 | 61 60 59 58
9| H0_jumpup_0|NOD| | => | 1 2 3 4 | 61 60 59 58
10| | | | => | 2 3 4 5 | 60 59 58 57
11| | | | => | 2 3 4 5 | 60 59 58 57
12| H0_jumpdown_4|NOD| | => | 3 4 5 6 | 59 58 57 56
13| | | | => | 3 4 5 6 | 59 58 57 56
14| | | | => | 4 5 6 7 | 58 57 56 55
15| | | | => | 4 5 6 7 | 58 57 56 55
---------------------------------------------------------------------------
===========================================================================
< Block [ 5] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|---------⌨️ 快捷键说明
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