📄 tcd1208_driver.prd
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< Block [ 1] > Node-Pin Assignments
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+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 1] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| H0_countc_5|NOD| | => | 5 6 7 0 | 7 6 5 12
1| H0_countc_9|NOD| | => | 5 6 7 0 | 7 6 5 12
2| | | | => | 6 7 0 1 | 6 5 12 11
3| | | | => | 6 7 0 1 | 6 5 12 11
4| H0_countc_1|NOD| | => | 7 0 1 2 | 5 12 11 10
5| H0_countc_8|NOD| | => | 7 0 1 2 | 5 12 11 10
6| | | | => | 0 1 2 3 | 12 11 10 9
7| | | | => | 0 1 2 3 | 12 11 10 9
8| H0_countc_0|NOD| | => | 1 2 3 4 | 11 10 9 8
9| H0_jumpup_8|NOD| | => | 1 2 3 4 | 11 10 9 8
10| | | | => | 2 3 4 5 | 10 9 8 7
11| | | | => | 2 3 4 5 | 10 9 8 7
12| D0_GoutDFFRH|NOD| | => | 3 4 5 6 | 9 8 7 6
13| | | | => | 3 4 5 6 | 9 8 7 6
14| | | | => | 4 5 6 7 | 8 7 6 5
15| | | | => | 4 5 6 7 | 8 7 6 5
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< Block [ 1] > IO-to-Node Pin Mapping
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+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
0| | | | 12| => | 0 1 2 3 4 5 6 7
1| | | | 11| => | 2 3 4 5 6 7 8 9
2| | | | 10| => | 4 5 6 7 8 9 10 11
3| | | | 9| => | 6 7 8 9 10 11 12 13
4| | | | 8| => | 8 9 10 11 12 13 14 15
5| | | | 7| => | 10 11 12 13 14 15 0 1
6| | | | 6| => | 12 13 14 15 0 1 2 3
7| reset|INP|*| 5| => | 14 15 0 1 2 3 4 5
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< Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table
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+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Input Macrocell and Node Pairs
_|_________________|__|___|_____|__________________________________________
0| | | | 12| => | Input macrocell [ -]
1| | | | 11| => | Input macrocell [ -]
2| | | | 10| => | Input macrocell [ -]
3| | | | 9| => | Input macrocell [ -]
4| | | | 8| => | Input macrocell [ -]
5| | | | 7| => | Input macrocell [ -]
6| | | | 6| => | Input macrocell [ -]
7| reset|INP|*| 5| => | Input macrocell [ -]
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< Block [ 1] > Input Multiplexer (IMX) Assignments
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+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 12| -| | ]
[RegIn 0 |126| -| | ]
[MCell 0 |125|NOD H0_countc_5| |*]
[MCell 1 |127|NOD H0_countc_9| |*]
1 [IOpin 1 | 11| -| | ]
[RegIn 1 |129| -| | ]
[MCell 2 |128| -| | ]
[MCell 3 |130| -| | ]
2 [IOpin 2 | 10| -| | ]
[RegIn 2 |132| -| | ]
[MCell 4 |131|NOD H0_countc_1| |*]
[MCell 5 |133|NOD H0_countc_8| |*]
3 [IOpin 3 | 9| -| | ]
[RegIn 3 |135| -| | ]
[MCell 6 |134| -| | ]
[MCell 7 |136| -| | ]
4 [IOpin 4 | 8| -| | ]
[RegIn 4 |138| -| | ]
[MCell 8 |137|NOD H0_countc_0| |*]
[MCell 9 |139|NOD H0_jumpup_8| |*]
5 [IOpin 5 | 7| -| | ]
[RegIn 5 |141| -| | ]
[MCell 10 |140| -| | ]
[MCell 11 |142| -| | ]
6 [IOpin 6 | 6| -| | ]
[RegIn 6 |144| -| | ]
[MCell 12 |143|NOD D0_GoutDFFRH| |*]
[MCell 13 |145| -| | ]
7 [IOpin 7 | 5|INP reset|*|*]
[RegIn 7 |147| -| | ]
[MCell 14 |146| -| | ]
[MCell 15 |148| -| | ]
---------------------------------------------------------------------------
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< Block [ 1] > Logic Array Fan-in
===========================================================================
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| Mcel 1 5 ( 133)| H0_countc_8
Mux01| Mcel 1 12 ( 143)| D0_GoutDFFRH
Mux02| IOPin 1 7 ( 5)| reset
Mux03| ... | ...
Mux04| ... | ...
Mux05| Mcel 5 0 ( 221)| P0_countc_0
Mux06| Mcel 4 4 ( 203)| H0_countc_11
Mux07| Mcel 4 0 ( 197)| H0_countc_2
Mux08| Mcel 4 8 ( 209)| H0_countc_7
Mux09| Mcel 2 0 ( 149)| H0_countc_4
Mux10| Mcel 4 12 ( 215)| H0_countc_3
Mux11| ... | ...
Mux12| ... | ...
Mux13| Mcel 4 1 ( 199)| H0_countc_6
Mux14| ... | ...
Mux15| ... | ...
Mux16| ... | ...
Mux17| Mcel 1 8 ( 137)| H0_countc_0
Mux18| ... | ...
Mux19| ... | ...
Mux20| Mcel 6 0 ( 245)| RN_gout
Mux21| ... | ...
Mux22| ... | ...
Mux23| ... | ...
Mux24| ... | ...
Mux25| ... | ...
Mux26| Mcel 1 0 ( 125)| H0_countc_5
Mux27| Mcel 1 4 ( 131)| H0_countc_1
Mux28| ... | ...
Mux29| ... | ...
Mux30| ... | ...
Mux31| ... | ...
Mux32| ... | ...
---------------------------------------------------------------------------
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< Block [ 2] > Macrocell (MCell) Cluster Assignments
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
| Sync/Async-------+ | | | Cluster to Mcell Assignment
| Node Fixed(*)----+ | | | | | +- XOR PT Size
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| H0_countc_4|NOD| | A | 1 :+: 1| 2 to [ 0]| 1 XOR to [ 0]
1| H0_jumpup_4|NOD| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| H0_LatchDFFRH|NOD| | A | 2 | 2 to [ 4]| 1 XOR free
5| H0_jumpup_3|NOD| | A | 1 | 2 free | 1 XOR to [ 5] for 1 PT sig
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8| C0_GoutDFFRH|NOD| | A | 1 | 2 free | 1 XOR to [ 8] for 1 PT sig
9| | ? | | S | | 4 free | 1 XOR free
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| H0_jumpup_6|NOD| | A | 1 | 2 free | 1 XOR to [12] for 1 PT sig
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
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< Block [ 2] > Maximum PT Capacity
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+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| H0_countc_4|NOD| | A | 1 :+: 1|=> can support up to [ 9] logic PT(s)
1| H0_jumpup_4|NOD| | A | 1 |=> can support up to [ 13] logic PT(s)
2| | ? | | S | |=> can support up to [ 12] logic PT(s)
3| | ? | | S | |=> can support up to [ 12] logic PT(s)
4| H0_LatchDFFRH|NOD| | A | 2 |=> can support up to [ 15] logic PT(s)
5| H0_jumpup_3|NOD| | A | 1 |=> can support up to [ 13] logic PT(s)
6| | ? | | S | |=> can support up to [ 14] logic PT(s)
7| | ? | | S | |=> can support up to [ 17] logic PT(s)
8| C0_GoutDFFRH|NOD| | A | 1 |=> can support up to [ 18] logic PT(s)
9| | ? | | S | |=> can support up to [ 17] logic PT(s)
10| | ? | | S | |=> can support up to [ 17] logic PT(s)
11| | ? | | S | |=> can support up to [ 17] logic PT(s)
12| H0_jumpup_6|NOD| | A | 1 |=> can support up to [ 18] logic PT(s)
13| | ? | | S | |=> can support up to [ 17] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
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< Block [ 2] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 2] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| H0_countc_4|NOD| | => | 5 6 7 0 | 24 25 26 19
1| H0_jumpup_4|NOD| | => | 5 6 7 0 | 24 25 26 19
2| | | | => | 6 7 0 1 | 25 26 19 20
3| | | | => | 6 7 0 1 | 25 26 19 20
4| H0_LatchDFFRH|NOD| | => | 7 0 1 2 | 26 19 20 21
5| H0_jumpup_3|NOD| | => | 7 0 1 2 | 26 19 20 21
6| | | | => | 0 1 2 3 | 19 20 21 22
7| | | | => | 0 1 2 3 | 19 20 21 22
8| C0_GoutDFFRH|NOD| | => | 1 2 3 4 | 20 21 22 23
9| | | | => | 1 2 3 4 | 20 21 22 23
10| | | | => | 2 3 4 5 | 21 22 23 24
11| | | | => | 2 3 4 5 | 21 22 23 24
12| H0_jumpup_6|NOD| | => | 3 4 5 6 | 22 23 24 25
13| | | | => | 3 4 5 6 | 22 23 24 25
14| | | | => | 4 5 6 7 | 23 24 25 26
15| | | | => | 4 5 6 7 | 23 24 25 26
---------------------------------------------------------------------------
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< Block [ 2] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 19| -| | ]
[RegIn 0 |150| -| | ]
[MCell 0 |149|NOD H0_countc_4| |*]
[MCell 1 |151|NOD H0_jumpup_4| |*]
1 [IOpin 1 | 20| -| | ]
[RegIn 1 |153| -| | ]
[MCell 2 |152| -| | ]
[MCell 3 |154| -| | ]
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