📄 tcd1208_driver.prd
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0| | ? | | S | | 4 free | 1 XOR free
1| | ? | | S | | 4 free | 1 XOR free
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| data2| IO| | A |13 | 2 to [ 4]| 1 XOR to [ 4] as logic PT
5| | ? | | S | | 4 to [ 4]| 1 XOR to [ 4] as logic PT
6| | ? | | S | | 4 to [ 4]| 1 XOR to [ 4] as logic PT
7| | ? | | S | | 4 free | 1 XOR free
8| data1| IO| | A |13 | 2 to [ 8]| 1 XOR to [ 8] as logic PT
9| | ? | | S | | 4 to [ 8]| 1 XOR to [ 8] as logic PT
10| | ? | | S | | 4 to [ 8]| 1 XOR to [ 8] as logic PT
11| | ? | | S | | 4 free | 1 XOR free
12| | ? | | S | | 4 free | 1 XOR free
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| | ? | | S | |=> can support up to [ 15] logic PT(s)
1| | ? | | S | |=> can support up to [ 20] logic PT(s)
2| | ? | | S | |=> can support up to [ 15] logic PT(s)
3| | ? | | S | |=> can support up to [ 10] logic PT(s)
4| data2| IO| | A |13 |=> can support up to [ 18] logic PT(s)
5| | ? | | S | |=> can support up to [ 5] logic PT(s)
6| | ? | | S | |=> can support up to [ 5] logic PT(s)
7| | ? | | S | |=> can support up to [ 5] logic PT(s)
8| data1| IO| | A |13 |=> can support up to [ 18] logic PT(s)
9| | ? | | S | |=> can support up to [ 5] logic PT(s)
10| | ? | | S | |=> can support up to [ 10] logic PT(s)
11| | ? | | S | |=> can support up to [ 15] logic PT(s)
12| | ? | | S | |=> can support up to [ 20] logic PT(s)
13| | ? | | S | |=> can support up to [ 20] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > Node-Pin Assignments
===========================================================================
+ Macrocell Number
| Node Fixed(*)------+
| Sig Type---+ | to | Block [ 0] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| | | | => | 5 6 7 0 | 98 99 100 93
1| | | | => | 5 6 7 0 | 98 99 100 93
2| | | | => | 6 7 0 1 | 99 100 93 94
3| | | | => | 6 7 0 1 | 99 100 93 94
4| data2| IO| | => | 7 0 ( 1) 2 | 100 93 ( 94) 95
5| | | | => | 7 0 1 2 | 100 93 94 95
6| | | | => | 0 1 2 3 | 93 94 95 96
7| | | | => | 0 1 2 3 | 93 94 95 96
8| data1| IO| | => | 1 2 ( 3) 4 | 94 95 ( 96) 97
9| | | | => | 1 2 3 4 | 94 95 96 97
10| | | | => | 2 3 4 5 | 95 96 97 98
11| | | | => | 2 3 4 5 | 95 96 97 98
12| | | | => | 3 4 5 6 | 96 97 98 99
13| | | | => | 3 4 5 6 | 96 97 98 99
14| | | | => | 4 5 6 7 | 97 98 99 100
15| | | | => | 4 5 6 7 | 97 98 99 100
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > IO-to-Node Pin Mapping
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Node Destinations Via Output Matrix
_|_________________|__|___|_____|___________________________________________
0| dclk|INP|*| 93| => | 0 1 2 3 4 5 6 7
1| data2| IO|*| 94| => | 2 3 ( 4) 5 6 7 8 9
2| askdata|INP|*| 95| => | 4 5 6 7 8 9 10 11
3| data1| IO|*| 96| => | 6 7 ( 8) 9 10 11 12 13
4| | | | 97| => | 8 9 10 11 12 13 14 15
5| | | | 98| => | 10 11 12 13 14 15 0 1
6| | | | 99| => | 12 13 14 15 0 1 2 3
7| | | |100| => | 14 15 0 1 2 3 4 5
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > IO/Node and IO/Input Macrocell Pairing Table
===========================================================================
+- Block IO Pin
| Device Pin No.--------+
| Pin Fixed(*)----+ |
| Sig Type--+ | | |
| Signal Name | | | | Input Macrocell and Node Pairs
_|_________________|__|___|_____|__________________________________________
0| dclk|INP|*| 93| => | Input macrocell [ -]
1| data2| IO|*| 94| => | Input macrocell [ -]
| | | | | | IO paired w/ node [ RN_data2]
2| askdata|INP|*| 95| => | Input macrocell [ -]
3| data1| IO|*| 96| => | Input macrocell [ -]
| | | | | | IO paired w/ node [ RN_data1]
4| | | | 97| => | Input macrocell [ -]
5| | | | 98| => | Input macrocell [ -]
6| | | | 99| => | Input macrocell [ -]
7| | | |100| => | Input macrocell [ -]
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > Input Multiplexer (IMX) Assignments
===========================================================================
+----- IO pin/Input Register, or Macrocell
IMX No. | +---- Block IO Pin or Macrocell Number
| | | ABEL Node/ +-- Signal using the Pin or Macrocell
| | | Pin Number | +- Signal Fixed (*) to Pin/Mcell
| | | | Sig Type | | +- Feedback Required (*)
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 93|INP dclk|*|*]
[RegIn 0 |102| -| | ]
[MCell 0 |101| -| | ]
[MCell 1 |103| -| | ]
1 [IOpin 1 | 94| IO data2|*| ] paired w/[ RN_data2]
[RegIn 1 |105| -| | ]
[MCell 2 |104| -| | ]
[MCell 3 |106| -| | ]
2 [IOpin 2 | 95|INP askdata|*|*]
[RegIn 2 |108| -| | ]
[MCell 4 |107|NOD RN_data2| |*] paired w/[ data2]
[MCell 5 |109| -| | ]
3 [IOpin 3 | 96| IO data1|*| ] paired w/[ RN_data1]
[RegIn 3 |111| -| | ]
[MCell 6 |110| -| | ]
[MCell 7 |112| -| | ]
4 [IOpin 4 | 97| -| | ]
[RegIn 4 |114| -| | ]
[MCell 8 |113|NOD RN_data1| |*] paired w/[ data1]
[MCell 9 |115| -| | ]
5 [IOpin 5 | 98| -| | ]
[RegIn 5 |117| -| | ]
[MCell 10 |116| -| | ]
[MCell 11 |118| -| | ]
6 [IOpin 6 | 99| -| | ]
[RegIn 6 |120| -| | ]
[MCell 12 |119| -| | ]
[MCell 13 |121| -| | ]
7 [IOpin 7 |100| -| | ]
[RegIn 7 |123| -| | ]
[MCell 14 |122| -| | ]
[MCell 15 |124| -| | ]
---------------------------------------------------------------------------
===========================================================================
< Block [ 0] > Logic Array Fan-in
===========================================================================
+- Central Switch Matrix No.
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| IOPin 6 5 ( 74)| addr3
Mux01| Mcel 0 4 ( 107)| RN_data2
Mux02| Mcel 6 4 ( 251)| H0_jumpdown_11
Mux03| IOPin 0 2 ( 95)| askdata
Mux04| IOPin 6 3 ( 72)| addr1
Mux05| Mcel 3 12 ( 191)| H0_jumpdown_1
Mux06| Mcel 1 9 ( 139)| H0_jumpup_8
Mux07| Mcel 3 5 ( 181)| H0_jumpup_10
Mux08| Mcel 7 12 ( 287)| H0_jumpup_11
Mux09| Mcel 5 5 ( 229)| H0_jumpup_1
Mux10| Mcel 5 1 ( 223)| H0_jumpdown_3
Mux11| IOPin 0 0 ( 93)| dclk
Mux12| Mcel 7 1 ( 271)| H0_jumpup_7
Mux13| Mcel 6 8 ( 257)| H0_jumpdown_5
Mux14| Mcel 6 12 ( 263)| H0_jumpdown_2
Mux15| IOPin 6 4 ( 73)| addr2
Mux16| Mcel 3 8 ( 185)| H0_jumpdown_6
Mux17| Mcel 3 1 ( 175)| H0_jumpdown_0
Mux18| Mcel 0 8 ( 113)| RN_data1
Mux19| IOPin 6 2 ( 71)| addr0
Mux20| Mcel 5 8 ( 233)| H0_jumpdown_7
Mux21| Mcel 3 4 ( 179)| H0_jumpdown_9
Mux22| Mcel 6 5 ( 253)| H0_jumpup_2
Mux23| Mcel 2 12 ( 167)| H0_jumpup_6
Mux24| Mcel 6 1 ( 247)| H0_jumpup_9
Mux25| Mcel 3 9 ( 187)| H0_jumpup_5
Mux26| Mcel 3 0 ( 173)| H0_jumpdown_10
Mux27| ... | ...
Mux28| Mcel 2 5 ( 157)| H0_jumpup_3
Mux29| Mcel 5 4 ( 227)| H0_jumpdown_8
Mux30| Mcel 2 1 ( 151)| H0_jumpup_4
Mux31| Mcel 5 12 ( 239)| H0_jumpdown_4
Mux32| Mcel 5 9 ( 235)| H0_jumpup_0
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Macrocell (MCell) Cluster Assignments
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size
| Sync/Async-------+ | | | Cluster to Mcell Assignment
| Node Fixed(*)----+ | | | | | +- XOR PT Size
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| H0_countc_5|NOD| | A | 2 | 2 to [ 0]| 1 XOR free
1| H0_countc_9|NOD| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| H0_countc_1|NOD| | A | 2 | 2 to [ 4]| 1 XOR free
5| H0_countc_8|NOD| | A | 1 | 2 free | 1 XOR to [ 5] for 1 PT sig
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
8| H0_countc_0|NOD| | A | 1 | 2 free | 1 XOR to [ 8] for 1 PT sig
9| H0_jumpup_8|NOD| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| D0_GoutDFFRH|NOD| | A | 1 | 2 free | 1 XOR to [12] for 1 PT sig
13| | ? | | S | | 4 free | 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
===========================================================================
< Block [ 1] > Maximum PT Capacity
===========================================================================
+ Macrocell Number
| PT Requirements------ Logic XOR+
| Sync/Async-------+ | |
| Node Fixed(*)----+ | | |
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
0| H0_countc_5|NOD| | A | 2 |=> can support up to [ 10] logic PT(s)
1| H0_countc_9|NOD| | A | 1 |=> can support up to [ 13] logic PT(s)
2| | ? | | S | |=> can support up to [ 12] logic PT(s)
3| | ? | | S | |=> can support up to [ 12] logic PT(s)
4| H0_countc_1|NOD| | A | 2 |=> can support up to [ 15] logic PT(s)
5| H0_countc_8|NOD| | A | 1 |=> can support up to [ 13] logic PT(s)
6| | ? | | S | |=> can support up to [ 14] logic PT(s)
7| | ? | | S | |=> can support up to [ 14] logic PT(s)
8| H0_countc_0|NOD| | A | 1 |=> can support up to [ 15] logic PT(s)
9| H0_jumpup_8|NOD| | A | 1 |=> can support up to [ 15] logic PT(s)
10| | ? | | S | |=> can support up to [ 14] logic PT(s)
11| | ? | | S | |=> can support up to [ 17] logic PT(s)
12| D0_GoutDFFRH|NOD| | A | 1 |=> can support up to [ 18] logic PT(s)
13| | ? | | S | |=> can support up to [ 17] logic PT(s)
14| | ? | | S | |=> can support up to [ 15] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
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