counter2plus.vm

汽车四轮定位CCD驱动CPLD源代码

//
// Written by Synplify
// Sat Apr 19 17:35:47 2003
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\isptools\synpbase\lib\vhd\std.vhd "
// file 2 "\e:\tcd-1208\2003.4.19\counter2plus.vhd "
// file 3 "\d:\isptools\synpbase\lib\vhd\std1164.vhd "

`timescale 100 ps/100 ps
module MACH_DFF (
  Q,
  D,
  CLK,
  R,
  S,
  NOTIFIER
);
output Q;
input D;
input CLK;
input R;
input S;
input NOTIFIER;
wire Q ;
wire D ;
wire CLK ;
wire R ;
wire S ;
wire NOTIFIER ;
wire un0 ;
wire un1 ;
wire true ;
wire false ;
  assign #(1)  un0 = ~ S;
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  reg r_e_g0; // dffrs
  always @(posedge CLK or posedge un1 or posedge un0 )
    r_e_g0 = #1 un1 ? 1'b0 : (un0 ? 1'b1 : D );
  assign Q = r_e_g0;
endmodule /* MACH_DFF */

module DFFRH (
  Q,
  D,
  CLK,
  R
);
output Q;
input D;
input CLK;
input R;
wire Q ;
wire D ;
wire CLK ;
wire R ;
wire un0 ;
wire un1 ;
wire true ;
wire notifier ;
wire false ;
  MACH_DFF INS1 (
	.Q(un0),
	.D(D),
	.CLK(CLK),
	.R(un1),
	.S(true),
	.NOTIFIER(notifier)
);
  assign #(1)  un1 = ~ R;
  assign true = 1'b1;
  assign false = 1'b0;
  assign notifier = 1'b0;
assign Q = un0;
endmodule /* DFFRH */

module IBUF (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* IBUF */

module OBUF (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* OBUF */

module AND2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  & I1 ;
endmodule /* AND2 */

module XOR2 (
  O,
  I0,
  I1
);
output O;
input I0;
input I1;
wire O ;
wire I0 ;
wire I1 ;
wire true ;
wire false ;
  assign true = 1'b1;
  assign false = 1'b0;
  assign #(1)  O = I0  ^ I1 ;
endmodule /* XOR2 */

module INV (
  O,
  I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
  assign #(1)  O = ~ I0;
  assign true = 1'b1;
  assign false = 1'b0;
endmodule /* INV */

module counter2plus (
  clk,
  reset,
  RS,
  Gout
);
input clk;
input reset;
output RS;
output Gout;
wire clk ;
wire reset ;
wire RS ;
wire Gout ;
wire [1:1] countc;
wire [31:31] un6_countc;
wire [1:0] countc_i;
wire [0:0] countc_c;
wire temprs_6 ;
wire clk_c ;
wire reset_c ;
wire RS_c ;
wire GND ;
wire VCC ;
// @2:19
  DFFRH \countc[0]  (
	.Q(countc_c[0]),
	.D(countc_i[0]),
	.CLK(clk_c),
	.R(reset_c)
);
// @2:19
  DFFRH \countc_Z[1]  (
	.Q(countc[1]),
	.D(un6_countc[31]),
	.CLK(clk_c),
	.R(reset_c)
);
  IBUF clk_Z (
	.O(clk_c),
	.I0(clk)
);
  IBUF reset_Z (
	.O(reset_c),
	.I0(reset)
);
// @2:19
  DFFRH RSDFFRH (
	.Q(RS_c),
	.D(temprs_6),
	.CLK(clk_c),
	.R(reset_c)
);
  OBUF RS_Z (
	.O(RS),
	.I0(RS_c)
);
  OBUF Gout_Z (
	.O(Gout),
	.I0(countc_c[0])
);
  AND2 temprs_6_Z (
	.O(temprs_6),
	.I0(countc_c[0]),
	.I1(countc_i[1])
);
  XOR2 G_3 (
	.O(un6_countc[31]),
	.I0(countc[1]),
	.I1(countc_c[0])
);
  INV \countc_i_Z[0]  (
	.O(countc_i[0]),
	.I0(countc_c[0])
);
  INV \countc_i_Z[1]  (
	.O(countc_i[1]),
	.I0(countc[1])
);
  assign GND = 1'b0;
  assign VCC = 1'b1;
endmodule /* counter2plus */