driver.vhm

汽车四轮定位CCD驱动CPLD源代码

    O => \G_109.UN3\,
    I0 => ASKDATA_C);
  \II_G_109.M\: AND2 port map (
    O => \G_109.UN1\,
    I0 => JUMPDOWN(9),
    I1 => ASKDATA_C);
  \II_G_109.N\: AND2 port map (
    O => \G_109.UN0\,
    I0 => COUNTC(9),
    I1 => \G_109.UN3\);
  \II_G_109.P\: OR2 port map (
    O => N_120,
    I0 => \G_109.UN1\,
    I1 => \G_109.UN0\);
  \II_G_110.R\: INV port map (
    O => \G_110.UN3\,
    I0 => ASKDATA_C);
  \II_G_110.M\: AND2 port map (
    O => \G_110.UN1\,
    I0 => JUMPDOWN(10),
    I1 => ASKDATA_C);
  \II_G_110.N\: AND2 port map (
    O => \G_110.UN0\,
    I0 => COUNTC(10),
    I1 => \G_110.UN3\);
  \II_G_110.P\: OR2 port map (
    O => N_121,
    I0 => \G_110.UN1\,
    I1 => \G_110.UN0\);
  \II_G_111.R\: INV port map (
    O => \G_111.UN3\,
    I0 => ASKDATA_C);
  \II_G_111.M\: AND2 port map (
    O => \G_111.UN1\,
    I0 => JUMPDOWN(11),
    I1 => ASKDATA_C);
  \II_G_111.N\: AND2 port map (
    O => \G_111.UN0\,
    I0 => COUNTC(11),
    I1 => \G_111.UN3\);
  \II_G_111.P\: OR2 port map (
    O => N_122,
    I0 => \G_111.UN1\,
    I1 => \G_111.UN0\);
  \II_G_112.R\: INV port map (
    O => \G_112.UN3\,
    I0 => ASKDATA_C);
  \II_G_112.M\: AND2 port map (
    O => \G_112.UN1\,
    I0 => DATA2_14,
    I1 => ASKDATA_C);
  \II_G_112.N\: AND2 port map (
    O => \G_112.UN0\,
    I0 => DATA2_C,
    I1 => \G_112.UN3\);
  \II_G_112.P\: OR2 port map (
    O => N_123,
    I0 => \G_112.UN1\,
    I1 => \G_112.UN0\);
  \II_G_113.R\: INV port map (
    O => \G_113.UN3\,
    I0 => ASKDATA_C);
  \II_G_113.M\: AND2 port map (
    O => \G_113.UN1\,
    I0 => DATA1_14,
    I1 => ASKDATA_C);
  \II_G_113.N\: AND2 port map (
    O => \G_113.UN0\,
    I0 => DATA1_C,
    I1 => \G_113.UN3\);
  \II_G_113.P\: OR2 port map (
    O => N_124,
    I0 => \G_113.UN1\,
    I1 => \G_113.UN0\);
  II_G_116: AND2 port map (
    O => N_168,
    I0 => COUNTC(2),
    I1 => N_106_I);
  II_G_22: AND2 port map (
    O => N_55,
    I0 => COUNTC(9),
    I1 => N_52);
  II_G_23: XOR2 port map (
    O => UN6_COUNTC(22),
    I0 => COUNTC(10),
    I1 => N_55);
  II_G_24: AND2 port map (
    O => N_58,
    I0 => COUNTC(10),
    I1 => N_55);
  II_G_25: XOR2 port map (
    O => UN6_COUNTC(21),
    I0 => COUNTC(11),
    I1 => N_58);
  II_TEMPSH_5_F0_I: AND2 port map (
    O => N_89_I,
    I0 => N_129_I,
    I1 => N_130_I);
  II_TEMPEFFICIANT_4_F0_0: AND2 port map (
    O => N_182,
    I0 => N_131_I,
    I1 => N_132_I);
  \II_COUNTC_6_I[3]\: AND2 port map (
    O => N_92_I,
    I0 => UN6_COUNTC(29),
    I1 => N_133_I);
  \II_COUNTC_6_I[5]\: AND2 port map (
    O => N_94_I,
    I0 => N_133_I,
    I1 => UN6_COUNTC(27));
  \II_COUNTC_6_I[7]\: AND2 port map (
    O => N_96_I,
    I0 => N_133_I,
    I1 => UN6_COUNTC(25));
  \II_COUNTC_6_I[11]\: AND2 port map (
    O => N_98_I,
    I0 => N_133_I,
    I1 => UN6_COUNTC(21));
  II_G_93: AND2 port map (
    O => N_104_I,
    I0 => COUNTC(7),
    I1 => COUNTC(11));
  II_G_94: AND2 port map (
    O => N_105_I_0,
    I0 => COUNTC(5),
    I1 => N_104_I);
  II_G_95: AND2 port map (
    O => N_106_I,
    I0 => COUNTC(1),
    I1 => N_105_I_0);
  II_G_96: AND2 port map (
    O => N_107_I_0,
    I0 => COUNTC_I_0(0),
    I1 => COUNTC_I_0(1));
  II_G_97: AND2 port map (
    O => N_108_I_0,
    I0 => COUNTC(0),
    I1 => N_106_I);
  II_G_7: XOR2 port map (
    O => UN6_COUNTC(30),
    I0 => COUNTC(2),
    I1 => N_31);
  II_G_8: AND2 port map (
    O => N_34,
    I0 => COUNTC(2),
    I1 => N_31);
  II_G_9: XOR2 port map (
    O => UN6_COUNTC(29),
    I0 => COUNTC(3),
    I1 => N_34);
  II_G_10: AND2 port map (
    O => N_37,
    I0 => COUNTC(3),
    I1 => N_34);
  II_G_11: XOR2 port map (
    O => UN6_COUNTC(28),
    I0 => COUNTC(4),
    I1 => N_37);
  II_G_12: AND2 port map (
    O => N_40,
    I0 => COUNTC(4),
    I1 => N_37);
  II_G_13: XOR2 port map (
    O => UN6_COUNTC(27),
    I0 => COUNTC(5),
    I1 => N_40);
  II_G_14: AND2 port map (
    O => N_43,
    I0 => COUNTC(5),
    I1 => N_40);
  II_G_15: XOR2 port map (
    O => UN6_COUNTC(26),
    I0 => COUNTC(6),
    I1 => N_43);
  II_G_16: AND2 port map (
    O => N_46,
    I0 => COUNTC(6),
    I1 => N_43);
  II_G_17: XOR2 port map (
    O => UN6_COUNTC(25),
    I0 => COUNTC(7),
    I1 => N_46);
  II_G_18: AND2 port map (
    O => N_49,
    I0 => COUNTC(7),
    I1 => N_46);
  II_G_19: XOR2 port map (
    O => UN6_COUNTC(24),
    I0 => COUNTC(8),
    I1 => N_49);
  II_G_20: AND2 port map (
    O => N_52,
    I0 => COUNTC(8),
    I1 => N_49);
  II_G_21: XOR2 port map (
    O => UN6_COUNTC(23),
    I0 => COUNTC(9),
    I1 => N_52);
  \II_DATA1_14_10_0.R\: INV port map (
    O => \DATA1_14_10_0.UN3\,
    I0 => ADDR1_C);
  \II_DATA1_14_10_0.M\: AND2 port map (
    O => \DATA1_14_10_0.UN1\,
    I0 => N_9,
    I1 => ADDR1_C);
  \II_DATA1_14_10_0.N\: AND2 port map (
    O => \DATA1_14_10_0.UN0\,
    I0 => N_8,
    I1 => \DATA1_14_10_0.UN3\);
  \II_DATA1_14_10_0.P\: OR2 port map (
    O => N_10,
    I0 => \DATA1_14_10_0.UN1\,
    I1 => \DATA1_14_10_0.UN0\);
  \II_DATA1_14_12_0.R\: INV port map (
    O => \DATA1_14_12_0.UN3\,
    I0 => ADDR3_C);
  \II_DATA1_14_12_0.M\: AND2 port map (
    O => \DATA1_14_12_0.UN1\,
    I0 => N_166,
    I1 => ADDR3_C);
  \II_DATA1_14_12_0.N\: AND2 port map (
    O => \DATA1_14_12_0.UN0\,
    I0 => N_7,
    I1 => \DATA1_14_12_0.UN3\);
  \II_DATA1_14_12_0.P\: OR2 port map (
    O => DATA1_14,
    I0 => \DATA1_14_12_0.UN1\,
    I1 => \DATA1_14_12_0.UN0\);
  \II_DATA2_14_1_0.R\: INV port map (
    O => \DATA2_14_1_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA2_14_1_0.M\: AND2 port map (
    O => \DATA2_14_1_0.UN1\,
    I0 => JUMPDOWN(1),
    I1 => ADDR0_C);
  \II_DATA2_14_1_0.N\: AND2 port map (
    O => \DATA2_14_1_0.UN0\,
    I0 => JUMPDOWN(0),
    I1 => \DATA2_14_1_0.UN3\);
  \II_DATA2_14_1_0.P\: OR2 port map (
    O => N_13,
    I0 => \DATA2_14_1_0.UN1\,
    I1 => \DATA2_14_1_0.UN0\);
  \II_DATA2_14_2_0.R\: INV port map (
    O => \DATA2_14_2_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA2_14_2_0.M\: AND2 port map (
    O => \DATA2_14_2_0.UN1\,
    I0 => JUMPDOWN(3),
    I1 => ADDR0_C);
  \II_DATA2_14_2_0.N\: AND2 port map (
    O => \DATA2_14_2_0.UN0\,
    I0 => JUMPDOWN(2),
    I1 => \DATA2_14_2_0.UN3\);
  \II_DATA2_14_2_0.P\: OR2 port map (
    O => N_14,
    I0 => \DATA2_14_2_0.UN1\,
    I1 => \DATA2_14_2_0.UN0\);
  \II_DATA2_14_3_0.R\: INV port map (
    O => \DATA2_14_3_0.UN3\,
    I0 => ADDR1_C);
  \II_DATA2_14_3_0.M\: AND2 port map (
    O => \DATA2_14_3_0.UN1\,
    I0 => N_14,
    I1 => ADDR1_C);
  \II_DATA2_14_3_0.N\: AND2 port map (
    O => \DATA2_14_3_0.UN0\,
    I0 => N_13,
    I1 => \DATA2_14_3_0.UN3\);
  \II_DATA2_14_3_0.P\: OR2 port map (
    O => N_15,
    I0 => \DATA2_14_3_0.UN1\,
    I1 => \DATA2_14_3_0.UN0\);
  \II_DATA2_14_4_0.R\: INV port map (
    O => \DATA2_14_4_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA2_14_4_0.M\: AND2 port map (
    O => \DATA2_14_4_0.UN1\,
    I0 => JUMPDOWN(5),
    I1 => ADDR0_C);
  \II_DATA2_14_4_0.N\: AND2 port map (
    O => \DATA2_14_4_0.UN0\,
    I0 => JUMPDOWN(4),
    I1 => \DATA2_14_4_0.UN3\);
  \II_DATA2_14_4_0.P\: OR2 port map (
    O => N_16,
    I0 => \DATA2_14_4_0.UN1\,
    I1 => \DATA2_14_4_0.UN0\);
  \II_DATA2_14_5_0.R\: INV port map (
    O => \DATA2_14_5_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA2_14_5_0.M\: AND2 port map (
    O => \DATA2_14_5_0.UN1\,
    I0 => JUMPDOWN(7),
    I1 => ADDR0_C);
  \II_DATA2_14_5_0.N\: AND2 port map (
    O => \DATA2_14_5_0.UN0\,
    I0 => JUMPDOWN(6),
    I1 => \DATA2_14_5_0.UN3\);
  \II_DATA2_14_5_0.P\: OR2 port map (
    O => N_17,
    I0 => \DATA2_14_5_0.UN1\,
    I1 => \DATA2_14_5_0.UN0\);
  \II_DATA2_14_6_0.R\: INV port map (
    O => \DATA2_14_6_0.UN3\,
    I0 => ADDR1_C);
  \II_DATA2_14_6_0.M\: AND2 port map (
    O => \DATA2_14_6_0.UN1\,
    I0 => N_17,
    I1 => ADDR1_C);
  \II_DATA2_14_6_0.N\: AND2 port map (
    O => \DATA2_14_6_0.UN0\,
    I0 => N_16,
    I1 => \DATA2_14_6_0.UN3\);
  \II_DATA2_14_6_0.P\: OR2 port map (
    O => N_18,
    I0 => \DATA2_14_6_0.UN1\,
    I1 => \DATA2_14_6_0.UN0\);
  \II_DATA2_14_7_0.R\: INV port map (
    O => \DATA2_14_7_0.UN3\,
    I0 => ADDR2_C);
  \II_DATA2_14_7_0.M\: AND2 port map (
    O => \DATA2_14_7_0.UN1\,
    I0 => N_18,
    I1 => ADDR2_C);
  \II_DATA2_14_7_0.N\: AND2 port map (
    O => \DATA2_14_7_0.UN0\,
    I0 => N_15,
    I1 => \DATA2_14_7_0.UN3\);
  \II_DATA2_14_7_0.P\: OR2 port map (
    O => N_19,
    I0 => \DATA2_14_7_0.UN1\,
    I1 => \DATA2_14_7_0.UN0\);
  \II_DATA2_14_8_0.R\: INV port map (
    O => \DATA2_14_8_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA2_14_8_0.M\: AND2 port map (
    O => \DATA2_14_8_0.UN1\,
    I0 => JUMPDOWN(9),
    I1 => ADDR0_C);
  \II_DATA2_14_8_0.N\: AND2 port map (
    O => \DATA2_14_8_0.UN0\,
    I0 => JUMPDOWN(8),
    I1 => \DATA2_14_8_0.UN3\);
  \II_DATA2_14_8_0.P\: OR2 port map (
    O => N_20,
    I0 => \DATA2_14_8_0.UN1\,
    I1 => \DATA2_14_8_0.UN0\);
  \II_DATA2_14_9_0.R\: INV port map (
    O => \DATA2_14_9_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA2_14_9_0.M\: AND2 port map (
    O => \DATA2_14_9_0.UN1\,
    I0 => JUMPDOWN(11),
    I1 => ADDR0_C);
  \II_DATA2_14_9_0.N\: AND2 port map (
    O => \DATA2_14_9_0.UN0\,
    I0 => JUMPDOWN(10),
    I1 => \DATA2_14_9_0.UN3\);
  \II_DATA2_14_9_0.P\: OR2 port map (
    O => N_21,
    I0 => \DATA2_14_9_0.UN1\,
    I1 => \DATA2_14_9_0.UN0\);
  \II_DATA2_14_10_0.R\: INV port map (
    O => \DATA2_14_10_0.UN3\,
    I0 => ADDR1_C);
  \II_DATA2_14_10_0.M\: AND2 port map (
    O => \DATA2_14_10_0.UN1\,
    I0 => N_21,
    I1 => ADDR1_C);
  \II_DATA2_14_10_0.N\: AND2 port map (
    O => \DATA2_14_10_0.UN0\,
    I0 => N_20,
    I1 => \DATA2_14_10_0.UN3\);
  \II_DATA2_14_10_0.P\: OR2 port map (
    O => N_22,
    I0 => \DATA2_14_10_0.UN1\,
    I1 => \DATA2_14_10_0.UN0\);
  \II_DATA2_14_12_0.R\: INV port map (
    O => \DATA2_14_12_0.UN3\,
    I0 => ADDR3_C);
  \II_DATA2_14_12_0.M\: AND2 port map (
    O => \DATA2_14_12_0.UN1\,
    I0 => N_167,
    I1 => ADDR3_C);
  \II_DATA2_14_12_0.N\: AND2 port map (
    O => \DATA2_14_12_0.UN0\,
    I0 => N_19,
    I1 => \DATA2_14_12_0.UN3\);
  \II_DATA2_14_12_0.P\: OR2 port map (
    O => DATA2_14,
    I0 => \DATA2_14_12_0.UN1\,
    I1 => \DATA2_14_12_0.UN0\);
  II_G_5: XOR2 port map (
    O => UN6_COUNTC(31),
    I0 => COUNTC(1),
    I1 => COUNTC(0));
  II_G_6: AND2 port map (
    O => N_31,
    I0 => COUNTC(1),
    I1 => COUNTC(0));
  \II_DATA1_14_1_0.R\: INV port map (
    O => \DATA1_14_1_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA1_14_1_0.M\: AND2 port map (
    O => \DATA1_14_1_0.UN1\,
    I0 => JUMPUP(1),
    I1 => ADDR0_C);
  \II_DATA1_14_1_0.N\: AND2 port map (
    O => \DATA1_14_1_0.UN0\,
    I0 => JUMPUP(0),
    I1 => \DATA1_14_1_0.UN3\);
  \II_DATA1_14_1_0.P\: OR2 port map (
    O => N_1,
    I0 => \DATA1_14_1_0.UN1\,
    I1 => \DATA1_14_1_0.UN0\);
  \II_DATA1_14_2_0.R\: INV port map (
    O => \DATA1_14_2_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA1_14_2_0.M\: AND2 port map (
    O => \DATA1_14_2_0.UN1\,
    I0 => JUMPUP(3),
    I1 => ADDR0_C);
  \II_DATA1_14_2_0.N\: AND2 port map (
    O => \DATA1_14_2_0.UN0\,
    I0 => JUMPUP(2),
    I1 => \DATA1_14_2_0.UN3\);
  \II_DATA1_14_2_0.P\: OR2 port map (
    O => N_2,
    I0 => \DATA1_14_2_0.UN1\,
    I1 => \DATA1_14_2_0.UN0\);
  \II_DATA1_14_3_0.R\: INV port map (
    O => \DATA1_14_3_0.UN3\,
    I0 => ADDR1_C);
  \II_DATA1_14_3_0.M\: AND2 port map (
    O => \DATA1_14_3_0.UN1\,
    I0 => N_2,
    I1 => ADDR1_C);
  \II_DATA1_14_3_0.N\: AND2 port map (
    O => \DATA1_14_3_0.UN0\,
    I0 => N_1,
    I1 => \DATA1_14_3_0.UN3\);
  \II_DATA1_14_3_0.P\: OR2 port map (
    O => N_3,
    I0 => \DATA1_14_3_0.UN1\,
    I1 => \DATA1_14_3_0.UN0\);
  \II_DATA1_14_4_0.R\: INV port map (
    O => \DATA1_14_4_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA1_14_4_0.M\: AND2 port map (
    O => \DATA1_14_4_0.UN1\,
    I0 => JUMPUP(5),
    I1 => ADDR0_C);
  \II_DATA1_14_4_0.N\: AND2 port map (
    O => \DATA1_14_4_0.UN0\,
    I0 => JUMPUP(4),
    I1 => \DATA1_14_4_0.UN3\);
  \II_DATA1_14_4_0.P\: OR2 port map (
    O => N_4,
    I0 => \DATA1_14_4_0.UN1\,
    I1 => \DATA1_14_4_0.UN0\);
  \II_DATA1_14_5_0.R\: INV port map (
    O => \DATA1_14_5_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA1_14_5_0.M\: AND2 port map (
    O => \DATA1_14_5_0.UN1\,
    I0 => JUMPUP(7),
    I1 => ADDR0_C);
  \II_DATA1_14_5_0.N\: AND2 port map (
    O => \DATA1_14_5_0.UN0\,
    I0 => JUMPUP(6),
    I1 => \DATA1_14_5_0.UN3\);
  \II_DATA1_14_5_0.P\: OR2 port map (
    O => N_5,
    I0 => \DATA1_14_5_0.UN1\,
    I1 => \DATA1_14_5_0.UN0\);
  \II_DATA1_14_6_0.R\: INV port map (
    O => \DATA1_14_6_0.UN3\,
    I0 => ADDR1_C);
  \II_DATA1_14_6_0.M\: AND2 port map (
    O => \DATA1_14_6_0.UN1\,
    I0 => N_5,
    I1 => ADDR1_C);
  \II_DATA1_14_6_0.N\: AND2 port map (
    O => \DATA1_14_6_0.UN0\,
    I0 => N_4,
    I1 => \DATA1_14_6_0.UN3\);
  \II_DATA1_14_6_0.P\: OR2 port map (
    O => N_6,
    I0 => \DATA1_14_6_0.UN1\,
    I1 => \DATA1_14_6_0.UN0\);
  \II_DATA1_14_7_0.R\: INV port map (
    O => \DATA1_14_7_0.UN3\,
    I0 => ADDR2_C);
  \II_DATA1_14_7_0.M\: AND2 port map (
    O => \DATA1_14_7_0.UN1\,
    I0 => N_6,
    I1 => ADDR2_C);
  \II_DATA1_14_7_0.N\: AND2 port map (
    O => \DATA1_14_7_0.UN0\,
    I0 => N_3,
    I1 => \DATA1_14_7_0.UN3\);
  \II_DATA1_14_7_0.P\: OR2 port map (
    O => N_7,
    I0 => \DATA1_14_7_0.UN1\,
    I1 => \DATA1_14_7_0.UN0\);
  \II_DATA1_14_8_0.R\: INV port map (
    O => \DATA1_14_8_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA1_14_8_0.M\: AND2 port map (
    O => \DATA1_14_8_0.UN1\,
    I0 => JUMPUP(9),
    I1 => ADDR0_C);
  \II_DATA1_14_8_0.N\: AND2 port map (
    O => \DATA1_14_8_0.UN0\,
    I0 => JUMPUP(8),
    I1 => \DATA1_14_8_0.UN3\);
  \II_DATA1_14_8_0.P\: OR2 port map (
    O => N_8,
    I0 => \DATA1_14_8_0.UN1\,
    I1 => \DATA1_14_8_0.UN0\);
  \II_DATA1_14_9_0.R\: INV port map (
    O => \DATA1_14_9_0.UN3\,
    I0 => ADDR0_C);
  \II_DATA1_14_9_0.M\: AND2 port map (
    O => \DATA1_14_9_0.UN1\,
    I0 => JUMPUP(11),
    I1 => ADDR0_C);
  \II_DATA1_14_9_0.N\: AND2 port map (
    O => \DATA1_14_9_0.UN0\,
    I0 => JUMPUP(10),
    I1 => \DATA1_14_9_0.UN3\);
  \II_DATA1_14_9_0.P\: OR2 port map (
    O => N_9,
    I0 => \DATA1_14_9_0.UN1\,
    I1 => \DATA1_14_9_0.UN0\);
  GND <= '0';
  VCC <= '1';
end beh;