driver.vhm

汽车四轮定位CCD驱动CPLD源代码

  component IBUF
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component AND2
    port(O :  out std_logic;
    I0 :  in std_logic;
    I1 :  in std_logic  );
  end component;
  component INV
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component OR2
    port(O :  out std_logic;
    I0 :  in std_logic;
    I1 :  in std_logic  );
  end component;
  component XOR2
    port(O :  out std_logic;
    I0 :  in std_logic;
    I1 :  in std_logic  );
  end component;
begin
  \II_JUMPDOWN[2]\: DFF port map (
    Q => JUMPDOWN(2),
    D => N_113,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[3]\: DFF port map (
    Q => JUMPDOWN(3),
    D => N_114,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[4]\: DFF port map (
    Q => JUMPDOWN(4),
    D => N_115,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[5]\: DFF port map (
    Q => JUMPDOWN(5),
    D => N_116,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[6]\: DFF port map (
    Q => JUMPDOWN(6),
    D => N_117,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[7]\: DFF port map (
    Q => JUMPDOWN(7),
    D => N_118,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[8]\: DFF port map (
    Q => JUMPDOWN(8),
    D => N_119,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[9]\: DFF port map (
    Q => JUMPDOWN(9),
    D => N_120,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[10]\: DFF port map (
    Q => JUMPDOWN(10),
    D => N_121,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[11]\: DFF port map (
    Q => JUMPDOWN(11),
    D => N_122,
    CLK => CCDIN_I_0);
  \II_COUNTC[11]\: DFFRH port map (
    Q => COUNTC(11),
    D => N_98_I,
    CLK => CLK_I_0,
    R => RESET_C);
  \II_JUMPUP[0]\: DFF port map (
    Q => JUMPUP(0),
    D => COUNTC(0),
    CLK => CCDIN_C);
  \II_JUMPUP[1]\: DFF port map (
    Q => JUMPUP(1),
    D => COUNTC(1),
    CLK => CCDIN_C);
  \II_JUMPUP[2]\: DFF port map (
    Q => JUMPUP(2),
    D => COUNTC(2),
    CLK => CCDIN_C);
  \II_JUMPUP[3]\: DFF port map (
    Q => JUMPUP(3),
    D => COUNTC(3),
    CLK => CCDIN_C);
  \II_JUMPUP[4]\: DFF port map (
    Q => JUMPUP(4),
    D => COUNTC(4),
    CLK => CCDIN_C);
  \II_JUMPUP[5]\: DFF port map (
    Q => JUMPUP(5),
    D => COUNTC(5),
    CLK => CCDIN_C);
  \II_JUMPUP[6]\: DFF port map (
    Q => JUMPUP(6),
    D => COUNTC(6),
    CLK => CCDIN_C);
  \II_JUMPUP[7]\: DFF port map (
    Q => JUMPUP(7),
    D => COUNTC(7),
    CLK => CCDIN_C);
  \II_JUMPUP[8]\: DFF port map (
    Q => JUMPUP(8),
    D => COUNTC(8),
    CLK => CCDIN_C);
  \II_JUMPUP[9]\: DFF port map (
    Q => JUMPUP(9),
    D => COUNTC(9),
    CLK => CCDIN_C);
  \II_JUMPUP[10]\: DFF port map (
    Q => JUMPUP(10),
    D => COUNTC(10),
    CLK => CCDIN_C);
  \II_JUMPUP[11]\: DFF port map (
    Q => JUMPUP(11),
    D => COUNTC(11),
    CLK => CCDIN_C);
  \II_JUMPDOWN[0]\: DFF port map (
    Q => JUMPDOWN(0),
    D => N_111,
    CLK => CCDIN_I_0);
  \II_JUMPDOWN[1]\: DFF port map (
    Q => JUMPDOWN(1),
    D => N_112,
    CLK => CCDIN_I_0);
  \II_COUNTC[0]\: DFFRH port map (
    Q => COUNTC(0),
    D => COUNTC_I_0(0),
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[1]\: DFFRH port map (
    Q => COUNTC(1),
    D => UN6_COUNTC(31),
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[2]\: DFFRH port map (
    Q => COUNTC(2),
    D => UN6_COUNTC(30),
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[3]\: DFFRH port map (
    Q => COUNTC(3),
    D => N_92_I,
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[4]\: DFFRH port map (
    Q => COUNTC(4),
    D => UN6_COUNTC(28),
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[5]\: DFFRH port map (
    Q => COUNTC(5),
    D => N_94_I,
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[6]\: DFFRH port map (
    Q => COUNTC(6),
    D => UN6_COUNTC(26),
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[7]\: DFFRH port map (
    Q => COUNTC(7),
    D => N_96_I,
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[8]\: DFFRH port map (
    Q => COUNTC(8),
    D => UN6_COUNTC(24),
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[9]\: DFFRH port map (
    Q => COUNTC(9),
    D => UN6_COUNTC(23),
    CLK => CLK_I_0,
    R => RESET_C);
  \II_COUNTC[10]\: DFFRH port map (
    Q => COUNTC(10),
    D => UN6_COUNTC(22),
    CLK => CLK_I_0,
    R => RESET_C);
  II_EFFICIANTDFFRH: DFFRH port map (
    Q => EFFICIANT_C,
    D => TEMPEFFICIANT_4,
    CLK => CLK_I_0,
    R => RESET_C);
  II_EFFICIANT: OBUF port map (
    O => Efficiant,
    I0 => EFFICIANT_C);
  II_LATCHDFFRH: DFFRH port map (
    Q => LATCH_C,
    D => TEMPLATCH_4,
    CLK => CLK_I_0,
    R => RESET_C);
  II_LATCH: OBUF port map (
    O => Latch,
    I0 => LATCH_C);
  II_SHDFFSH: DFFSH port map (
    Q => SH_C,
    D => N_89_I,
    CLK => CLK_I_0,
    S => RESET_C);
  II_SH: OBUF port map (
    O => SH,
    I0 => SH_C);
  II_DATA1DFF: DFF port map (
    Q => DATA1_C,
    D => N_124,
    CLK => DATACLK_C);
  II_DATA1: OBUF port map (
    O => data1,
    I0 => DATA1_C);
  II_DATA2DFF: DFF port map (
    Q => DATA2_C,
    D => N_123,
    CLK => DATACLK_C);
  II_DATA2: OBUF port map (
    O => data2,
    I0 => DATA2_C);
  II_CLK: IBUF port map (
    O => CLK_C,
    I0 => clk);
  II_RESET: IBUF port map (
    O => RESET_C,
    I0 => reset);
  II_CCDIN: IBUF port map (
    O => CCDIN_C,
    I0 => ccdin);
  II_ASKDATA: IBUF port map (
    O => ASKDATA_C,
    I0 => askdata);
  II_DATACLK: IBUF port map (
    O => DATACLK_C,
    I0 => dataclk);
  II_ADDR0: IBUF port map (
    O => ADDR0_C,
    I0 => addr0);
  II_ADDR1: IBUF port map (
    O => ADDR1_C,
    I0 => addr1);
  II_ADDR2: IBUF port map (
    O => ADDR2_C,
    I0 => addr2);
  II_ADDR3: IBUF port map (
    O => ADDR3_C,
    I0 => addr3);
  \II_TEMPEFFICIANT_4_F0_0_AND2_0.G_138\: AND2 port map (
    O => N_202,
    I0 => N_198,
    I1 => N_197);
  \II_TEMPEFFICIANT_4_F0_0_AND2_0.G_139\: AND2 port map (
    O => N_203,
    I0 => N_202,
    I1 => N_201);
  II_TEMPEFFICIANT_4_F0_0_I: INV port map (
    O => TEMPEFFICIANT_4,
    I0 => N_182);
  II_N_129_I: INV port map (
    O => N_129_I,
    I0 => N_129);
  II_N_130_I: INV port map (
    O => N_130_I,
    I0 => N_130);
  II_G_99: AND2 port map (
    O => N_110_I_0,
    I0 => N_107_I_0,
    I1 => N_194);
  II_G_115: AND2 port map (
    O => N_169,
    I0 => N_110_I_0,
    I1 => N_195);
  II_TEMPEFFICIANT_4_F0_0_AND2_0: AND2 port map (
    O => N_132,
    I0 => N_110_I_0,
    I1 => N_203);
  II_TEMPSH_5_F0_I_AND2_0: AND2 port map (
    O => N_130,
    I0 => N_105_I_0,
    I1 => N_196);
  \II_G_99.G_130\: AND2 port map (
    O => N_194,
    I0 => COUNTC_I_0(2),
    I1 => COUNTC(3));
  \II_G_115.G_131\: AND2 port map (
    O => N_195,
    I0 => COUNTC(4),
    I1 => N_104_I);
  \II_TEMPSH_5_F0_I_AND2_0.G_132\: AND2 port map (
    O => N_196,
    I0 => COUNTC(2),
    I1 => N_107_I_0);
  \II_TEMPEFFICIANT_4_F0_0_AND2_0.G_133\: AND2 port map (
    O => N_197,
    I0 => COUNTC(5),
    I1 => COUNTC_I_0(4));
  \II_TEMPEFFICIANT_4_F0_0_AND2_0.G_134\: AND2 port map (
    O => N_198,
    I0 => COUNTC_I_0(7),
    I1 => COUNTC_I_0(11));
  \II_TEMPEFFICIANT_4_F0_0_AND2_0.G_135\: AND2 port map (
    O => N_199,
    I0 => COUNTC_I_0(8),
    I1 => COUNTC_I_0(6));
  \II_TEMPEFFICIANT_4_F0_0_AND2_0.G_136\: AND2 port map (
    O => N_200,
    I0 => COUNTC_I_0(10),
    I1 => COUNTC_I_0(9));
  \II_TEMPEFFICIANT_4_F0_0_AND2_0.G_137\: AND2 port map (
    O => N_201,
    I0 => N_200,
    I1 => N_199);
  II_G_116_I: INV port map (
    O => N_127,
    I0 => N_168);
  II_G_115_I: INV port map (
    O => N_126,
    I0 => N_169);
  II_G_97_I: INV port map (
    O => N_108,
    I0 => N_108_I_0);
  II_N_133_I: INV port map (
    O => N_133_I,
    I0 => N_133);
  II_N_131_I: INV port map (
    O => N_131_I,
    I0 => N_131);
  II_N_132_I: INV port map (
    O => N_132_I,
    I0 => N_132);
  II_SH_I: INV port map (
    O => SH_I_0,
    I0 => SH_C);
  \II_COUNTC_I[0]\: INV port map (
    O => COUNTC_I_0(0),
    I0 => COUNTC(0));
  \II_COUNTC_I[1]\: INV port map (
    O => COUNTC_I_0(1),
    I0 => COUNTC(1));
  II_CLK_I: INV port map (
    O => CLK_I_0,
    I0 => CLK_C);
  II_CCDIN_I: INV port map (
    O => CCDIN_I_0,
    I0 => CCDIN_C);
  II_TEMPSH_5_F0_I_AND2: AND2 port map (
    O => N_129,
    I0 => SH_I_0,
    I1 => N_127);
  II_TEMPEFFICIANT_4_F0_0_AND2: AND2 port map (
    O => N_131,
    I0 => EFFICIANT_C,
    I1 => N_126);
  \II_COUNTC_6_I_AND2[3]\: AND2 port map (
    O => N_133,
    I0 => COUNTC(2),
    I1 => N_108_I_0);
  \II_TEMPLATCH_4_F0_0_MUX2.R\: INV port map (
    O => \TEMPLATCH_4_F0_0_MUX2.UN3\,
    I0 => N_108);
  \II_TEMPLATCH_4_F0_0_MUX2.M\: AND2 port map (
    O => \TEMPLATCH_4_F0_0_MUX2.UN1\,
    I0 => LATCH_C,
    I1 => N_108);
  \II_TEMPLATCH_4_F0_0_MUX2.N\: AND2 port map (
    O => \TEMPLATCH_4_F0_0_MUX2.UN0\,
    I0 => COUNTC_I_0(2),
    I1 => \TEMPLATCH_4_F0_0_MUX2.UN3\);
  \II_TEMPLATCH_4_F0_0_MUX2.P\: OR2 port map (
    O => TEMPLATCH_4,
    I0 => \TEMPLATCH_4_F0_0_MUX2.UN1\,
    I1 => \TEMPLATCH_4_F0_0_MUX2.UN0\);
  II_DATA1_14_11_0_0_AND2: AND2 port map (
    O => N_166,
    I0 => ADDR2_I,
    I1 => N_10);
  II_DATA2_14_11_0_0_AND2: AND2 port map (
    O => N_167,
    I0 => ADDR2_I,
    I1 => N_22);
  \II_COUNTC_I[8]\: INV port map (
    O => COUNTC_I_0(8),
    I0 => COUNTC(8));
  \II_COUNTC_I[6]\: INV port map (
    O => COUNTC_I_0(6),
    I0 => COUNTC(6));
  \II_COUNTC_I[10]\: INV port map (
    O => COUNTC_I_0(10),
    I0 => COUNTC(10));
  \II_COUNTC_I[9]\: INV port map (
    O => COUNTC_I_0(9),
    I0 => COUNTC(9));
  \II_COUNTC_I[4]\: INV port map (
    O => COUNTC_I_0(4),
    I0 => COUNTC(4));
  \II_COUNTC_I[7]\: INV port map (
    O => COUNTC_I_0(7),
    I0 => COUNTC(7));
  \II_COUNTC_I[11]\: INV port map (
    O => COUNTC_I_0(11),
    I0 => COUNTC(11));
  II_ADDR2_I: INV port map (
    O => ADDR2_I,
    I0 => ADDR2_C);
  \II_COUNTC_I[2]\: INV port map (
    O => COUNTC_I_0(2),
    I0 => COUNTC(2));
  \II_G_100.R\: INV port map (
    O => \G_100.UN3\,
    I0 => ASKDATA_C);
  \II_G_100.M\: AND2 port map (
    O => \G_100.UN1\,
    I0 => JUMPDOWN(0),
    I1 => ASKDATA_C);
  \II_G_100.N\: AND2 port map (
    O => \G_100.UN0\,
    I0 => COUNTC(0),
    I1 => \G_100.UN3\);
  \II_G_100.P\: OR2 port map (
    O => N_111,
    I0 => \G_100.UN1\,
    I1 => \G_100.UN0\);
  \II_G_101.R\: INV port map (
    O => \G_101.UN3\,
    I0 => ASKDATA_C);
  \II_G_101.M\: AND2 port map (
    O => \G_101.UN1\,
    I0 => JUMPDOWN(1),
    I1 => ASKDATA_C);
  \II_G_101.N\: AND2 port map (
    O => \G_101.UN0\,
    I0 => COUNTC(1),
    I1 => \G_101.UN3\);
  \II_G_101.P\: OR2 port map (
    O => N_112,
    I0 => \G_101.UN1\,
    I1 => \G_101.UN0\);
  \II_G_102.R\: INV port map (
    O => \G_102.UN3\,
    I0 => ASKDATA_C);
  \II_G_102.M\: AND2 port map (
    O => \G_102.UN1\,
    I0 => JUMPDOWN(2),
    I1 => ASKDATA_C);
  \II_G_102.N\: AND2 port map (
    O => \G_102.UN0\,
    I0 => COUNTC(2),
    I1 => \G_102.UN3\);
  \II_G_102.P\: OR2 port map (
    O => N_113,
    I0 => \G_102.UN1\,
    I1 => \G_102.UN0\);
  \II_G_103.R\: INV port map (
    O => \G_103.UN3\,
    I0 => ASKDATA_C);
  \II_G_103.M\: AND2 port map (
    O => \G_103.UN1\,
    I0 => JUMPDOWN(3),
    I1 => ASKDATA_C);
  \II_G_103.N\: AND2 port map (
    O => \G_103.UN0\,
    I0 => COUNTC(3),
    I1 => \G_103.UN3\);
  \II_G_103.P\: OR2 port map (
    O => N_114,
    I0 => \G_103.UN1\,
    I1 => \G_103.UN0\);
  \II_G_104.R\: INV port map (
    O => \G_104.UN3\,
    I0 => ASKDATA_C);
  \II_G_104.M\: AND2 port map (
    O => \G_104.UN1\,
    I0 => JUMPDOWN(4),
    I1 => ASKDATA_C);
  \II_G_104.N\: AND2 port map (
    O => \G_104.UN0\,
    I0 => COUNTC(4),
    I1 => \G_104.UN3\);
  \II_G_104.P\: OR2 port map (
    O => N_115,
    I0 => \G_104.UN1\,
    I1 => \G_104.UN0\);
  \II_G_105.R\: INV port map (
    O => \G_105.UN3\,
    I0 => ASKDATA_C);
  \II_G_105.M\: AND2 port map (
    O => \G_105.UN1\,
    I0 => JUMPDOWN(5),
    I1 => ASKDATA_C);
  \II_G_105.N\: AND2 port map (
    O => \G_105.UN0\,
    I0 => COUNTC(5),
    I1 => \G_105.UN3\);
  \II_G_105.P\: OR2 port map (
    O => N_116,
    I0 => \G_105.UN1\,
    I1 => \G_105.UN0\);
  \II_G_106.R\: INV port map (
    O => \G_106.UN3\,
    I0 => ASKDATA_C);
  \II_G_106.M\: AND2 port map (
    O => \G_106.UN1\,
    I0 => JUMPDOWN(6),
    I1 => ASKDATA_C);
  \II_G_106.N\: AND2 port map (
    O => \G_106.UN0\,
    I0 => COUNTC(6),
    I1 => \G_106.UN3\);
  \II_G_106.P\: OR2 port map (
    O => N_117,
    I0 => \G_106.UN1\,
    I1 => \G_106.UN0\);
  \II_G_107.R\: INV port map (
    O => \G_107.UN3\,
    I0 => ASKDATA_C);
  \II_G_107.M\: AND2 port map (
    O => \G_107.UN1\,
    I0 => JUMPDOWN(7),
    I1 => ASKDATA_C);
  \II_G_107.N\: AND2 port map (
    O => \G_107.UN0\,
    I0 => COUNTC(7),
    I1 => \G_107.UN3\);
  \II_G_107.P\: OR2 port map (
    O => N_118,
    I0 => \G_107.UN1\,
    I1 => \G_107.UN0\);
  \II_G_108.R\: INV port map (
    O => \G_108.UN3\,
    I0 => ASKDATA_C);
  \II_G_108.M\: AND2 port map (
    O => \G_108.UN1\,
    I0 => JUMPDOWN(8),
    I1 => ASKDATA_C);
  \II_G_108.N\: AND2 port map (
    O => \G_108.UN0\,
    I0 => COUNTC(8),
    I1 => \G_108.UN3\);
  \II_G_108.P\: OR2 port map (
    O => N_119,
    I0 => \G_108.UN1\,
    I1 => \G_108.UN0\);
  \II_G_109.R\: INV port map (