driver.vhm

汽车四轮定位CCD驱动CPLD源代码

--
-- Written by Synplicity
-- Sun Apr 20 15:12:14 2003
--

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity MACH_DFF is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  R :  in std_logic;
  S :  in std_logic;
  NOTIFIER :  in std_logic);
end MACH_DFF;

architecture beh of MACH_DFF is
  signal UN0 : std_logic ;
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  UN0 <= not S;
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  II_Q: prim_dff port map (Q, D, CLK, UN1, UN0);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity AND2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end AND2;

architecture beh of AND2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 and I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity DFF is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic);
end DFF;

architecture beh of DFF is
  signal NN_1 : std_logic ;
  signal NOTIFIER : std_logic ;
  signal NN_2 : std_logic ;
  component MACH_DFF
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic;
    S :  in std_logic;
    NOTIFIER :  in std_logic  );
  end component;
begin
  II_INS4: MACH_DFF port map (
    Q => Q,
    D => D,
    CLK => CLK,
    R => NN_1,
    S => NN_1,
    NOTIFIER => NOTIFIER);
  NN_1 <= '1';
  NN_2 <= '0';
  NOTIFIER <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity DFFRH is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  R :  in std_logic);
end DFFRH;

architecture beh of DFFRH is
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NOTIFIER : std_logic ;
  signal NN_2 : std_logic ;
  component MACH_DFF
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic;
    S :  in std_logic;
    NOTIFIER :  in std_logic  );
  end component;
begin
  II_INS1: MACH_DFF port map (
    Q => Q,
    D => D,
    CLK => CLK,
    R => UN1,
    S => NN_1,
    NOTIFIER => NOTIFIER);
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  NOTIFIER <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity DFFSH is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  S :  in std_logic);
end DFFSH;

architecture beh of DFFSH is
  signal NN_1 : std_logic ;
  signal UN1 : std_logic ;
  signal NOTIFIER : std_logic ;
  signal NN_2 : std_logic ;
  component MACH_DFF
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic;
    S :  in std_logic;
    NOTIFIER :  in std_logic  );
  end component;
begin
  II_INS5: MACH_DFF port map (
    Q => Q,
    D => D,
    CLK => CLK,
    R => NN_1,
    S => UN1,
    NOTIFIER => NOTIFIER);
  UN1 <= not S;
  NN_1 <= '1';
  NN_2 <= '0';
  NOTIFIER <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity IBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end IBUF;

architecture beh of IBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity INV is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end INV;

architecture beh of INV is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= not I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end OBUF;

architecture beh of OBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OR2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end OR2;

architecture beh of OR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 or I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity XOR2 is
port(
  O :  out std_logic;
  I0 :  in std_logic;
  I1 :  in std_logic);
end XOR2;

architecture beh of XOR2 is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I0 xor I1  after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity Driver is
port(
  Efficiant :  out std_logic;
  Latch :  out std_logic;
  SH :  out std_logic;
  data1 :  out std_logic;
  data2 :  out std_logic;
  clk :  in std_logic;
  reset :  in std_logic;
  ccdin :  in std_logic;
  askdata :  in std_logic;
  dataclk :  in std_logic;
  addr0 :  in std_logic;
  addr1 :  in std_logic;
  addr2 :  in std_logic;
  addr3 :  in std_logic);
end Driver;

architecture beh of Driver is
  signal COUNTC : std_logic_vector(11 downto 0);
  signal JUMPDOWN : std_logic_vector(11 downto 0);
  signal UN6_COUNTC : std_logic_vector(31 downto 21);
  signal JUMPUP : std_logic_vector(11 downto 0);
  signal COUNTC_I_0 : std_logic_vector(11 downto 0);
  signal TEMPEFFICIANT_4 : std_logic ;
  signal DATA1_14 : std_logic ;
  signal DATA2_14 : std_logic ;
  signal N_1 : std_logic ;
  signal N_2 : std_logic ;
  signal N_3 : std_logic ;
  signal N_4 : std_logic ;
  signal N_5 : std_logic ;
  signal N_6 : std_logic ;
  signal N_7 : std_logic ;
  signal N_8 : std_logic ;
  signal N_9 : std_logic ;
  signal N_10 : std_logic ;
  signal N_13 : std_logic ;
  signal N_14 : std_logic ;
  signal N_15 : std_logic ;
  signal N_16 : std_logic ;
  signal N_17 : std_logic ;
  signal N_18 : std_logic ;
  signal N_19 : std_logic ;
  signal N_20 : std_logic ;
  signal N_21 : std_logic ;
  signal N_22 : std_logic ;
  signal N_31 : std_logic ;
  signal N_34 : std_logic ;
  signal N_37 : std_logic ;
  signal N_40 : std_logic ;
  signal N_43 : std_logic ;
  signal N_46 : std_logic ;
  signal N_49 : std_logic ;
  signal N_52 : std_logic ;
  signal N_55 : std_logic ;
  signal N_58 : std_logic ;
  signal N_108 : std_logic ;
  signal N_111 : std_logic ;
  signal N_112 : std_logic ;
  signal N_113 : std_logic ;
  signal N_114 : std_logic ;
  signal N_115 : std_logic ;
  signal N_116 : std_logic ;
  signal N_117 : std_logic ;
  signal N_118 : std_logic ;
  signal N_119 : std_logic ;
  signal N_120 : std_logic ;
  signal N_121 : std_logic ;
  signal N_122 : std_logic ;
  signal N_123 : std_logic ;
  signal N_124 : std_logic ;
  signal N_126 : std_logic ;
  signal N_127 : std_logic ;
  signal N_129 : std_logic ;
  signal N_130 : std_logic ;
  signal N_131 : std_logic ;
  signal N_132 : std_logic ;
  signal N_133 : std_logic ;
  signal TEMPLATCH_4 : std_logic ;
  signal N_166 : std_logic ;
  signal N_167 : std_logic ;
  signal ADDR2_I : std_logic ;
  signal SH_I_0 : std_logic ;
  signal CLK_I_0 : std_logic ;
  signal CCDIN_I_0 : std_logic ;
  signal EFFICIANT_C : std_logic ;
  signal LATCH_C : std_logic ;
  signal SH_C : std_logic ;
  signal DATA1_C : std_logic ;
  signal DATA2_C : std_logic ;
  signal CLK_C : std_logic ;
  signal RESET_C : std_logic ;
  signal CCDIN_C : std_logic ;
  signal ASKDATA_C : std_logic ;
  signal DATACLK_C : std_logic ;
  signal ADDR0_C : std_logic ;
  signal ADDR1_C : std_logic ;
  signal ADDR2_C : std_logic ;
  signal ADDR3_C : std_logic ;
  signal N_168 : std_logic ;
  signal N_169 : std_logic ;
  signal N_133_I : std_logic ;
  signal N_131_I : std_logic ;
  signal N_132_I : std_logic ;
  signal N_182 : std_logic ;
  signal N_129_I : std_logic ;
  signal N_130_I : std_logic ;
  signal N_110_I_0 : std_logic ;
  signal N_108_I_0 : std_logic ;
  signal N_105_I_0 : std_logic ;
  signal N_107_I_0 : std_logic ;
  signal N_89_I : std_logic ;
  signal N_96_I : std_logic ;
  signal N_94_I : std_logic ;
  signal N_92_I : std_logic ;
  signal N_98_I : std_logic ;
  signal N_106_I : std_logic ;
  signal N_104_I : std_logic ;
  signal N_194 : std_logic ;
  signal N_195 : std_logic ;
  signal N_196 : std_logic ;
  signal N_197 : std_logic ;
  signal N_198 : std_logic ;
  signal N_199 : std_logic ;
  signal N_200 : std_logic ;
  signal N_201 : std_logic ;
  signal N_202 : std_logic ;
  signal N_203 : std_logic ;
  signal \TEMPLATCH_4_F0_0_MUX2.UN3\ : std_logic ;
  signal \TEMPLATCH_4_F0_0_MUX2.UN1\ : std_logic ;
  signal \TEMPLATCH_4_F0_0_MUX2.UN0\ : std_logic ;
  signal \G_100.UN3\ : std_logic ;
  signal \G_100.UN1\ : std_logic ;
  signal \G_100.UN0\ : std_logic ;
  signal \G_101.UN3\ : std_logic ;
  signal \G_101.UN1\ : std_logic ;
  signal \G_101.UN0\ : std_logic ;
  signal \G_102.UN3\ : std_logic ;
  signal \G_102.UN1\ : std_logic ;
  signal \G_102.UN0\ : std_logic ;
  signal \G_103.UN3\ : std_logic ;
  signal \G_103.UN1\ : std_logic ;
  signal \G_103.UN0\ : std_logic ;
  signal \G_104.UN3\ : std_logic ;
  signal \G_104.UN1\ : std_logic ;
  signal \G_104.UN0\ : std_logic ;
  signal \G_105.UN3\ : std_logic ;
  signal \G_105.UN1\ : std_logic ;
  signal \G_105.UN0\ : std_logic ;
  signal \G_106.UN3\ : std_logic ;
  signal \G_106.UN1\ : std_logic ;
  signal \G_106.UN0\ : std_logic ;
  signal \G_107.UN3\ : std_logic ;
  signal \G_107.UN1\ : std_logic ;
  signal \G_107.UN0\ : std_logic ;
  signal \G_108.UN3\ : std_logic ;
  signal \G_108.UN1\ : std_logic ;
  signal \G_108.UN0\ : std_logic ;
  signal \G_109.UN3\ : std_logic ;
  signal \G_109.UN1\ : std_logic ;
  signal \G_109.UN0\ : std_logic ;
  signal \G_110.UN3\ : std_logic ;
  signal \G_110.UN1\ : std_logic ;
  signal \G_110.UN0\ : std_logic ;
  signal \G_111.UN3\ : std_logic ;
  signal \G_111.UN1\ : std_logic ;
  signal \G_111.UN0\ : std_logic ;
  signal \G_112.UN3\ : std_logic ;
  signal \G_112.UN1\ : std_logic ;
  signal \G_112.UN0\ : std_logic ;
  signal \G_113.UN3\ : std_logic ;
  signal \G_113.UN1\ : std_logic ;
  signal \G_113.UN0\ : std_logic ;
  signal \DATA1_14_10_0.UN3\ : std_logic ;
  signal \DATA1_14_10_0.UN1\ : std_logic ;
  signal \DATA1_14_10_0.UN0\ : std_logic ;
  signal \DATA1_14_12_0.UN3\ : std_logic ;
  signal \DATA1_14_12_0.UN1\ : std_logic ;
  signal \DATA1_14_12_0.UN0\ : std_logic ;
  signal \DATA2_14_1_0.UN3\ : std_logic ;
  signal \DATA2_14_1_0.UN1\ : std_logic ;
  signal \DATA2_14_1_0.UN0\ : std_logic ;
  signal \DATA2_14_2_0.UN3\ : std_logic ;
  signal \DATA2_14_2_0.UN1\ : std_logic ;
  signal \DATA2_14_2_0.UN0\ : std_logic ;
  signal \DATA2_14_3_0.UN3\ : std_logic ;
  signal \DATA2_14_3_0.UN1\ : std_logic ;
  signal \DATA2_14_3_0.UN0\ : std_logic ;
  signal \DATA2_14_4_0.UN3\ : std_logic ;
  signal \DATA2_14_4_0.UN1\ : std_logic ;
  signal \DATA2_14_4_0.UN0\ : std_logic ;
  signal \DATA2_14_5_0.UN3\ : std_logic ;
  signal \DATA2_14_5_0.UN1\ : std_logic ;
  signal \DATA2_14_5_0.UN0\ : std_logic ;
  signal \DATA2_14_6_0.UN3\ : std_logic ;
  signal \DATA2_14_6_0.UN1\ : std_logic ;
  signal \DATA2_14_6_0.UN0\ : std_logic ;
  signal \DATA2_14_7_0.UN3\ : std_logic ;
  signal \DATA2_14_7_0.UN1\ : std_logic ;
  signal \DATA2_14_7_0.UN0\ : std_logic ;
  signal \DATA2_14_8_0.UN3\ : std_logic ;
  signal \DATA2_14_8_0.UN1\ : std_logic ;
  signal \DATA2_14_8_0.UN0\ : std_logic ;
  signal \DATA2_14_9_0.UN3\ : std_logic ;
  signal \DATA2_14_9_0.UN1\ : std_logic ;
  signal \DATA2_14_9_0.UN0\ : std_logic ;
  signal \DATA2_14_10_0.UN3\ : std_logic ;
  signal \DATA2_14_10_0.UN1\ : std_logic ;
  signal \DATA2_14_10_0.UN0\ : std_logic ;
  signal \DATA2_14_12_0.UN3\ : std_logic ;
  signal \DATA2_14_12_0.UN1\ : std_logic ;
  signal \DATA2_14_12_0.UN0\ : std_logic ;
  signal \DATA1_14_1_0.UN3\ : std_logic ;
  signal \DATA1_14_1_0.UN1\ : std_logic ;
  signal \DATA1_14_1_0.UN0\ : std_logic ;
  signal \DATA1_14_2_0.UN3\ : std_logic ;
  signal \DATA1_14_2_0.UN1\ : std_logic ;
  signal \DATA1_14_2_0.UN0\ : std_logic ;
  signal \DATA1_14_3_0.UN3\ : std_logic ;
  signal \DATA1_14_3_0.UN1\ : std_logic ;
  signal \DATA1_14_3_0.UN0\ : std_logic ;
  signal \DATA1_14_4_0.UN3\ : std_logic ;
  signal \DATA1_14_4_0.UN1\ : std_logic ;
  signal \DATA1_14_4_0.UN0\ : std_logic ;
  signal \DATA1_14_5_0.UN3\ : std_logic ;
  signal \DATA1_14_5_0.UN1\ : std_logic ;
  signal \DATA1_14_5_0.UN0\ : std_logic ;
  signal \DATA1_14_6_0.UN3\ : std_logic ;
  signal \DATA1_14_6_0.UN1\ : std_logic ;
  signal \DATA1_14_6_0.UN0\ : std_logic ;
  signal \DATA1_14_7_0.UN3\ : std_logic ;
  signal \DATA1_14_7_0.UN1\ : std_logic ;
  signal \DATA1_14_7_0.UN0\ : std_logic ;
  signal \DATA1_14_8_0.UN3\ : std_logic ;
  signal \DATA1_14_8_0.UN1\ : std_logic ;
  signal \DATA1_14_8_0.UN0\ : std_logic ;
  signal \DATA1_14_9_0.UN3\ : std_logic ;
  signal \DATA1_14_9_0.UN1\ : std_logic ;
  signal \DATA1_14_9_0.UN0\ : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component DFF
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic  );
  end component;
  component DFFRH
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic  );
  end component;
  component OBUF
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component DFFSH
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    S :  in std_logic  );
  end component;