tcd1208_driver.vho

汽车四轮定位CCD驱动CPLD源代码

  GATE_T_37_I_1:   AND2 port map ( O=>T_37, I1=>H0_jumpdown_2_Q, I0=>GATE_T_37_A );
  GATE_T_37_I_2:   INV port map ( O=>GATE_T_37_A, I0=>askdata_PIN );
  GATE_T_38_I_1:   AND2 port map ( O=>T_38, I1=>H0_countc_2_Q, I0=>askdata_PIN );
  GATE_T_39_I_1:   AND2 port map ( O=>T_39, I1=>H0_jumpdown_1_Q, I0=>GATE_T_39_A );
  GATE_T_39_I_2:   INV port map ( O=>GATE_T_39_A, I0=>askdata_PIN );
  GATE_T_40_I_1:   AND2 port map ( O=>T_40, I1=>H0_countc_1_Q, I0=>askdata_PIN );
  GATE_T_41_I_1:   AND2 port map ( O=>T_41, I1=>H0_countc_0_Q, I0=>askdata_PIN );
  GATE_T_42_I_1:   AND2 port map ( O=>T_42, I1=>H0_jumpdown_0_Q, I0=>GATE_T_42_A );
  GATE_T_42_I_2:   INV port map ( O=>GATE_T_42_A, I0=>askdata_PIN );
  GATE_T_43_I_1:   AND3 port map ( O=>T_43, I2=>T_122, I1=>T_123, I0=>T_121 );
  GATE_T_44_I_1:   AND4 port map ( O=>T_44, I3=>H0_countc_0_Q, I2=>H0_countc_3_Q, I1=>H0_countc_2_Q, I0=>H0_countc_1_Q );
  GATE_T_45_I_1:   NOR2 port map ( O=>T_45, I1=>H0_countc_0_Q, I0=>H0_countc_3_Q );
  GATE_T_46_I_1:   NOR2 port map ( O=>T_46, I1=>H0_countc_3_Q, I0=>H0_countc_2_Q );
  GATE_T_47_I_1:   NOR2 port map ( O=>T_47, I1=>H0_countc_3_Q, I0=>H0_countc_1_Q );
  GATE_T_48_I_1:   INV port map ( I0=>H0_countc_2_Q, O=>GATE_T_48_A );
  GATE_T_48_I_2:   AND3 port map ( O=>T_48, I2=>H0_countc_1_Q, I1=>H0_countc_0_Q, I0=>GATE_T_48_A );
  GATE_T_49_I_1:   AND2 port map ( O=>T_49, I1=>H0_countc_2_Q, I0=>GATE_T_49_A );
  GATE_T_49_I_2:   INV port map ( O=>GATE_T_49_A, I0=>H0_countc_0_Q );
  GATE_T_50_I_1:   AND2 port map ( O=>T_50, I1=>H0_countc_2_Q, I0=>GATE_T_50_A );
  GATE_T_50_I_2:   INV port map ( O=>GATE_T_50_A, I0=>H0_countc_1_Q );
  GATE_T_51_I_1:   AND4 port map ( O=>T_51, I3=>T_128, I2=>T_129, I1=>T_130, I0=>SH_Q );
  GATE_T_52_I_1:   AND4 port map ( O=>T_52, I3=>T_124, I2=>T_125, I1=>T_126, I0=>T_127 );
  GATE_T_53_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_53_A );
  GATE_T_53_I_2:   AND3 port map ( O=>T_53, I2=>T_150, I1=>T_149, I0=>GATE_T_53_A );
  GATE_T_54_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_54_A );
  GATE_T_54_I_2:   AND3 port map ( O=>T_54, I2=>T_148, I1=>T_147, I0=>GATE_T_54_A );
  GATE_T_55_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_55_A );
  GATE_T_55_I_2:   AND3 port map ( O=>T_55, I2=>T_146, I1=>T_145, I0=>GATE_T_55_A );
  GATE_T_56_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_56_A );
  GATE_T_56_I_2:   AND3 port map ( O=>T_56, I2=>T_144, I1=>T_143, I0=>GATE_T_56_A );
  GATE_T_57_I_1:   AND3 port map ( O=>T_57, I2=>T_142, I1=>H0_i_2_Q, I0=>T_141 );
  GATE_T_58_I_1:   AND3 port map ( O=>T_58, I2=>T_140, I1=>H0_i_2_Q, I0=>T_139 );
  GATE_T_59_I_1:   AND3 port map ( O=>T_59, I2=>T_138, I1=>H0_i_2_Q, I0=>T_137 );
  GATE_T_60_I_1:   AND3 port map ( O=>T_60, I2=>T_136, I1=>H0_i_2_Q, I0=>T_135 );
  GATE_T_61_I_3:   AND4 port map ( O=>T_61, I3=>H0_i_3_Q, I2=>H0_jumpdown_8_Q, I1=>GATE_T_61_B, I0=>GATE_T_61_A );
  GATE_T_61_I_2:   INV port map ( I0=>H0_i_0_Q, O=>GATE_T_61_B );
  GATE_T_61_I_1:   INV port map ( I0=>H0_i_1_Q, O=>GATE_T_61_A );
  GATE_T_62_I_1:   AND4 port map ( O=>T_62, I3=>H0_i_3_Q, I2=>H0_jumpdown_10_Q, I1=>H0_i_1_Q, I0=>GATE_T_62_A );
  GATE_T_62_I_2:   INV port map ( I0=>H0_i_0_Q, O=>GATE_T_62_A );
  GATE_T_63_I_1:   AND4 port map ( O=>T_63, I3=>H0_i_3_Q, I2=>H0_jumpdown_9_Q, I1=>H0_i_0_Q, I0=>GATE_T_63_A );
  GATE_T_63_I_2:   INV port map ( I0=>H0_i_1_Q, O=>GATE_T_63_A );
  GATE_T_64_I_1:   AND4 port map ( O=>T_64, I3=>H0_i_0_Q, I2=>H0_i_1_Q, I1=>H0_i_3_Q, I0=>H0_jumpdown_11_Q );
  GATE_T_65_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_65_A );
  GATE_T_65_I_2:   AND3 port map ( O=>T_65, I2=>T_170, I1=>T_169, I0=>GATE_T_65_A );
  GATE_T_66_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_66_A );
  GATE_T_66_I_2:   AND3 port map ( O=>T_66, I2=>T_168, I1=>T_167, I0=>GATE_T_66_A );
  GATE_T_67_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_67_A );
  GATE_T_67_I_2:   AND3 port map ( O=>T_67, I2=>T_166, I1=>T_165, I0=>GATE_T_67_A );
  GATE_T_68_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_68_A );
  GATE_T_68_I_2:   AND3 port map ( O=>T_68, I2=>T_164, I1=>T_163, I0=>GATE_T_68_A );
  GATE_T_69_I_1:   AND3 port map ( O=>T_69, I2=>T_162, I1=>H0_i_2_Q, I0=>T_161 );
  GATE_T_70_I_1:   AND3 port map ( O=>T_70, I2=>T_160, I1=>H0_i_2_Q, I0=>T_159 );
  GATE_T_71_I_1:   AND3 port map ( O=>T_71, I2=>T_158, I1=>H0_i_2_Q, I0=>T_157 );
  GATE_T_72_I_1:   AND3 port map ( O=>T_72, I2=>T_156, I1=>H0_i_2_Q, I0=>T_155 );
  GATE_T_73_I_3:   AND4 port map ( O=>T_73, I3=>H0_i_3_Q, I2=>H0_jumpup_8_Q, I1=>GATE_T_73_B, I0=>GATE_T_73_A );
  GATE_T_73_I_2:   INV port map ( I0=>H0_i_0_Q, O=>GATE_T_73_B );
  GATE_T_73_I_1:   INV port map ( I0=>H0_i_1_Q, O=>GATE_T_73_A );
  GATE_T_74_I_1:   AND4 port map ( O=>T_74, I3=>H0_i_3_Q, I2=>H0_jumpup_10_Q, I1=>H0_i_1_Q, I0=>GATE_T_74_A );
  GATE_T_74_I_2:   INV port map ( I0=>H0_i_0_Q, O=>GATE_T_74_A );
  GATE_T_75_I_1:   AND4 port map ( O=>T_75, I3=>H0_i_3_Q, I2=>H0_jumpup_9_Q, I1=>H0_i_0_Q, I0=>GATE_T_75_A );
  GATE_T_75_I_2:   INV port map ( I0=>H0_i_1_Q, O=>GATE_T_75_A );
  GATE_T_76_I_1:   AND4 port map ( O=>T_76, I3=>H0_i_0_Q, I2=>H0_i_1_Q, I1=>H0_i_3_Q, I0=>H0_jumpup_11_Q );
  GATE_T_77_I_1:   AND4 port map ( O=>T_77, I3=>H0_countc_0_Q, I2=>H0_countc_11_Q, I1=>H0_countc_7_Q, I0=>H0_countc_5_Q );
  GATE_T_78_I_14:   NOR4 port map ( O=>T_78, I3=>H0_countc_10_Q, I2=>H0_countc_9_Q, I1=>H0_countc_8_Q, I0=>H0_countc_6_Q );
  GATE_T_79_I_3:   AND4 port map ( O=>T_79, I3=>H0_countc_2_Q, I2=>H0_countc_1_Q, I1=>GATE_T_79_B, I0=>GATE_T_79_A );
  GATE_T_79_I_2:   INV port map ( I0=>H0_countc_4_Q, O=>GATE_T_79_B );
  GATE_T_79_I_1:   INV port map ( I0=>H0_countc_3_Q, O=>GATE_T_79_A );
  GATE_T_80_I_1:   AND4 port map ( O=>T_80, I3=>H0_countc_0_Q, I2=>H0_countc_11_Q, I1=>H0_countc_7_Q, I0=>H0_countc_5_Q );
  GATE_T_81_I_14:   NOR4 port map ( O=>T_81, I3=>H0_countc_10_Q, I2=>H0_countc_9_Q, I1=>H0_countc_8_Q, I0=>H0_countc_6_Q );
  GATE_T_82_I_1:   NOR4 port map ( I0=>H0_countc_3_Q, I1=>H0_countc_4_Q, O=>T_82, I2=>H0_countc_2_Q, I3=>GATE_T_82_DN );
  GATE_T_82_I_2:   INV port map ( I0=>H0_countc_1_Q, O=>GATE_T_82_DN );
  GATE_T_83_I_1:   AND2 port map ( O=>T_83, I1=>H0_i_0_Q, I0=>H0_i_1_Q );
  GATE_T_84_I_1:   AND2 port map ( O=>T_84, I1=>askdata_PIN, I0=>GATE_T_84_A );
  GATE_T_84_I_2:   INV port map ( O=>GATE_T_84_A, I0=>H0_i_3_Q );
  GATE_T_85_I_1:   AND2 port map ( O=>T_85, I1=>H0_countc_0_Q, I0=>H0_countc_7_Q );
  GATE_T_86_I_1:   AND3 port map ( O=>T_86, I2=>H0_countc_10_Q, I1=>H0_countc_9_Q, I0=>H0_countc_5_Q );
  GATE_T_87_I_1:   AND3 port map ( O=>T_87, I2=>H0_countc_6_Q, I1=>H0_countc_4_Q, I0=>H0_countc_8_Q );
  GATE_T_88_I_1:   AND3 port map ( O=>T_88, I2=>H0_countc_2_Q, I1=>H0_countc_1_Q, I0=>H0_countc_3_Q );
  GATE_T_89_I_1:   AND3 port map ( O=>T_89, I2=>H0_countc_11_Q, I1=>H0_countc_7_Q, I0=>H0_countc_0_Q );
  GATE_T_90_I_1:   INV port map ( I0=>H0_countc_10_Q, O=>GATE_T_90_A );
  GATE_T_90_I_2:   INV port map ( I0=>H0_countc_9_Q, O=>GATE_T_90_B );
  GATE_T_90_I_3:   AND3 port map ( O=>T_90, I0=>H0_countc_5_Q, I2=>GATE_T_90_A, I1=>GATE_T_90_B );
  GATE_T_91_I_1:   NOR3 port map ( O=>T_91, I2=>H0_countc_6_Q, I1=>H0_countc_4_Q, I0=>H0_countc_8_Q );
  GATE_T_92_I_1:   INV port map ( I0=>H0_countc_3_Q, O=>GATE_T_92_A );
  GATE_T_92_I_2:   AND3 port map ( O=>T_92, I2=>H0_countc_2_Q, I1=>H0_countc_1_Q, I0=>GATE_T_92_A );
  GATE_T_93_I_1:   AND2 port map ( O=>T_93, I1=>H0_countc_5_Q, I0=>H0_countc_6_Q );
  GATE_T_94_I_1:   AND2 port map ( O=>T_94, I1=>H0_countc_4_Q, I0=>H0_countc_3_Q );
  GATE_T_95_I_1:   AND2 port map ( O=>T_95, I1=>H0_countc_2_Q, I0=>H0_countc_1_Q );
  GATE_T_96_I_1:   AND3 port map ( O=>T_96, I2=>H0_countc_11_Q, I1=>H0_countc_7_Q, I0=>H0_countc_0_Q );
  GATE_T_97_I_1:   INV port map ( I0=>H0_countc_10_Q, O=>GATE_T_97_A );
  GATE_T_97_I_2:   INV port map ( I0=>H0_countc_9_Q, O=>GATE_T_97_B );
  GATE_T_97_I_3:   AND3 port map ( O=>T_97, I0=>H0_countc_5_Q, I2=>GATE_T_97_A, I1=>GATE_T_97_B );
  GATE_T_98_I_1:   NOR3 port map ( O=>T_98, I2=>H0_countc_6_Q, I1=>H0_countc_4_Q, I0=>H0_countc_8_Q );
  GATE_T_99_I_1:   INV port map ( I0=>H0_countc_3_Q, O=>GATE_T_99_A );
  GATE_T_99_I_2:   AND3 port map ( O=>T_99, I2=>H0_countc_2_Q, I1=>H0_countc_1_Q, I0=>GATE_T_99_A );
  GATE_T_100_I_1:   AND2 port map ( O=>T_100, I1=>H0_countc_4_Q, I0=>H0_countc_3_Q );
  GATE_T_101_I_1:   AND2 port map ( O=>T_101, I1=>H0_countc_2_Q, I0=>H0_countc_1_Q );
  GATE_T_102_I_1:   AND3 port map ( O=>T_102, I2=>H0_countc_11_Q, I1=>H0_countc_7_Q, I0=>H0_countc_0_Q );
  GATE_T_103_I_1:   INV port map ( I0=>H0_countc_10_Q, O=>GATE_T_103_A );
  GATE_T_103_I_2:   INV port map ( I0=>H0_countc_9_Q, O=>GATE_T_103_B );
  GATE_T_103_I_3:   AND3 port map ( O=>T_103, I0=>H0_countc_5_Q, I2=>GATE_T_103_A, I1=>GATE_T_103_B );
  GATE_T_104_I_1:   NOR3 port map ( O=>T_104, I2=>H0_countc_6_Q, I1=>H0_countc_4_Q, I0=>H0_countc_8_Q );
  GATE_T_105_I_1:   INV port map ( I0=>H0_countc_3_Q, O=>GATE_T_105_A );
  GATE_T_105_I_2:   AND3 port map ( O=>T_105, I2=>H0_countc_2_Q, I1=>H0_countc_1_Q, I0=>GATE_T_105_A );
  GATE_T_106_I_1:   AND3 port map ( O=>T_106, I2=>H0_countc_5_Q, I1=>H0_countc_9_Q, I0=>H0_countc_7_Q );
  GATE_T_107_I_1:   AND3 port map ( O=>T_107, I2=>H0_countc_6_Q, I1=>H0_countc_4_Q, I0=>H0_countc_8_Q );
  GATE_T_108_I_1:   AND3 port map ( O=>T_108, I2=>H0_countc_2_Q, I1=>H0_countc_1_Q, I0=>H0_countc_3_Q );
  GATE_T_109_I_1:   AND3 port map ( O=>T_109, I2=>H0_countc_7_Q, I1=>H0_countc_5_Q, I0=>H0_countc_0_Q );
  GATE_T_110_I_1:   AND3 port map ( O=>T_110, I2=>H0_countc_6_Q, I1=>H0_countc_4_Q, I0=>H0_countc_8_Q );
  GATE_T_111_I_1:   AND3 port map ( O=>T_111, I2=>H0_countc_2_Q, I1=>H0_countc_1_Q, I0=>H0_countc_3_Q );
  GATE_T_112_I_1:   AND2 port map ( O=>T_112, I1=>H0_countc_0_Q, I0=>H0_countc_7_Q );
  GATE_T_113_I_1:   AND2 port map ( O=>T_113, I1=>H0_countc_5_Q, I0=>H0_countc_6_Q );
  GATE_T_114_I_1:   AND2 port map ( O=>T_114, I1=>H0_countc_4_Q, I0=>H0_countc_3_Q );
  GATE_T_115_I_1:   AND2 port map ( O=>T_115, I1=>H0_countc_2_Q, I0=>H0_countc_1_Q );
  GATE_T_116_I_1:   AND2 port map ( O=>T_116, I1=>H0_countc_0_Q, I0=>H0_countc_5_Q );
  GATE_T_117_I_1:   AND2 port map ( O=>T_117, I1=>H0_countc_4_Q, I0=>H0_countc_3_Q );
  GATE_T_118_I_1:   AND2 port map ( O=>T_118, I1=>H0_countc_2_Q, I0=>H0_countc_1_Q );
  GATE_T_119_I_1:   OR2 port map ( O=>T_119, I1=>T_46, I0=>T_45 );
  GATE_T_120_I_1:   OR2 port map ( O=>T_120, I1=>T_44, I0=>T_43 );
  GATE_T_121_I_1:   AND3 port map ( O=>T_121, I2=>H0_countc_7_Q, I1=>H0_countc_5_Q, I0=>H0_countc_11_Q );
  GATE_T_122_I_1:   NOR3 port map ( O=>T_122, I2=>H0_countc_9_Q, I1=>H0_countc_8_Q, I0=>H0_countc_10_Q );
  GATE_T_123_I_1:   NOR3 port map ( O=>T_123, I2=>H0_countc_4_Q, I1=>H0_countc_3_Q, I0=>H0_countc_6_Q );
  GATE_T_124_I_1:   INV port map ( I0=>SH_Q, O=>GATE_T_124_A );
  GATE_T_124_I_2:   AND3 port map ( O=>T_124, I2=>H0_countc_11_Q, I1=>H0_countc_7_Q, I0=>GATE_T_124_A );
  GATE_T_125_I_1:   INV port map ( I0=>H0_countc_10_Q, O=>GATE_T_125_A );
  GATE_T_125_I_2:   INV port map ( I0=>H0_countc_9_Q, O=>GATE_T_125_B );
  GATE_T_125_I_3:   AND3 port map ( O=>T_125, I0=>H0_countc_5_Q, I2=>GATE_T_125_A, I1=>GATE_T_125_B );
  GATE_T_126_I_1:   NOR3 port map ( O=>T_126, I2=>H0_countc_6_Q, I1=>H0_countc_4_Q, I0=>H0_countc_8_Q );
  GATE_T_127_I_1:   INV port map ( I0=>H0_countc_3_Q, O=>GATE_T_127_A );
  GATE_T_127_I_2:   AND3 port map ( O=>T_127, I2=>H0_countc_2_Q, I1=>H0_countc_1_Q, I0=>GATE_T_127_A );
  GATE_T_128_I_1:   AND4 port map ( O=>T_128, I3=>H0_countc_7_Q, I2=>H0_countc_5_Q, I1=>H0_countc_11_Q, I0=>GATE_T_128_A );
  GATE_T_128_I_2:   INV port map ( I0=>H0_countc_0_Q, O=>GATE_T_128_A );
  GATE_T_129_I_14:   NOR4 port map ( O=>T_129, I3=>H0_countc_10_Q, I2=>H0_countc_9_Q, I1=>H0_countc_8_Q, I0=>H0_countc_6_Q );
  GATE_T_130_I_1:   NOR4 port map ( I0=>H0_countc_3_Q, I1=>H0_countc_4_Q, O=>T_130, I2=>H0_countc_1_Q, I3=>GATE_T_130_DN );
  GATE_T_130_I_2:   INV port map ( I0=>H0_countc_2_Q, O=>GATE_T_130_DN );
  GATE_T_131_I_1:   OR3 port map ( O=>T_131, I2=>T_63, I1=>T_62, I0=>T_64 );
  GATE_T_132_I_1:   OR3 port map ( O=>T_132, I2=>T_60, I1=>T_59, I0=>T_61 );
  GATE_T_133_I_1:   OR3 port map ( O=>T_133, I2=>T_57, I1=>T_56, I0=>T_58 );
  GATE_T_134_I_1:   OR3 port map ( O=>T_134, I2=>T_54, I1=>T_53, I0=>T_55 );
  GATE_T_135_I_1:   AND2 port map ( O=>T_135, I1=>H0_i_0_Q, I0=>H0_i_1_Q );
  GATE_T_136_I_1:   AND2 port map ( O=>T_136, I1=>H0_jumpdown_7_Q, I0=>GATE_T_136_A );
  GATE_T_136_I_2:   INV port map ( O=>GATE_T_136_A, I0=>H0_i_3_Q );
  GATE_T_137_I_1:   AND2 port map ( O=>T_137, I1=>H0_i_0_Q, I0=>GATE_T_137_A );
  GATE_T_137_I_2:   INV port map ( O=>GATE_T_137_A, I0=>H0_i_1_Q );
  GATE_T_138_I_1:   AND2 port map ( O=>T_138, I1=>H0_jumpdown_5_Q, I0=>GATE_T_138_A );
  GATE_T_138_I_2:   INV port map ( O=>GATE_T_138_A, I0=>H0_i_3_Q );
  GATE_T_139_I_1:   AND2 port map ( O=>T_139, I1=>H0_i_1_Q, I0=>GATE_T_139_A );
  GATE_T_139_I_2:   INV port map ( O=>GATE_T_139_A, I0=>H0_i_0_Q );
  GATE_T_140_I_1:   AND2 port map ( O=>T_140, I1=>H0_jumpdown_6_Q, I0=>GATE_T_140_A );
  GATE_T_140_I_2:   INV port map ( O=>GATE_T_140_A, I0=>H0_i_3_Q );
  GATE_T_141_I_1:   NOR2 port map ( O=>T_141, I1=>H0_i_0_Q, I0=>H0_i_1_Q );
  GATE_T_142_I_1:   AND2 port map ( O=>T_142, I1=>H0_jumpdown_4_Q, I0=>GATE_T_142_A );
  GATE_T_142_I_2:   INV port map ( O=>GATE_T_142_A, I0=>H0_i_3_Q );
  GATE_T_143_I_1:   AND2 port map ( O=>T_143, I1=>H0_i_0_Q, I0=>H0_i_1_Q );
  GATE_T_144_I_1:   AND2 port map ( O=>T_144, I1=>H0_jumpdown_3_Q, I0=>GATE_T_144_A );
  GATE_T_144_I_2:   INV port map ( O=>GATE_T_144_A, I0=>H0_i_3_Q );
  GATE_T_145_I_1:   AND2 port map ( O=>T_145, I1=>H0_i_0_Q, I0=>GATE_T_145_A );
  GATE_T_145_I_2:   INV port map ( O=>GATE_T_145_A, I0=>H0_i_1_Q );
  GATE_T_146_I_1:   AND2 port map ( O=>T_146, I1=>H0_jumpdown_1_Q, I0=>GATE_T_146_A );
  GATE_T_146_I_2:   INV port map ( O=>GATE_T_146_A, I0=>H0_i_3_Q );
  GATE_T_147_I_1:   AND2 port map ( O=>T_147, I1=>H0_i_1_Q, I0=>GATE_T_147_A );
  GATE_T_147_I_2:   INV port map ( O=>GATE_T_147_A, I0=>H0_i_0_Q );
  GATE_T_148_I_1:   AND2 port map ( O=>T_148, I1=>H0_jumpdown_2_Q, I0=>GATE_T_148_A );
  GATE_T_148_I_2:   INV port map ( O=>GATE_T_148_A, I0=>H0_i_3_Q );
  GATE_T_149_I_1:   NOR2 port map ( O=>T_149, I1=>H0_i_0_Q, I0=>H0_i_1_Q );
  GATE_T_150_I_1:   AND2 port map ( O=>T_150, I1=>H0_jumpdown_0_Q, I0=>GATE_T_150_A );
  GATE_T_150_I_2:   INV port map ( O=>GATE_T_150_A, I0=>H0_i_3_Q );
  GATE_T_151_I_1:   OR3 port map ( O=>T_151, I2=>T_75, I1=>T_74, I0=>T_76 );
  GATE_T_152_I_1:   OR3 port map ( O=>T_152, I2=>T_72, I1=>T_71, I0=>T_73 );
  GATE_T_153_I_1:   OR3 port map ( O=>T_153, I2=>T_69, I1=>T_68, I0=>T_70 );
  GATE_T_154_I_1:   OR3 port map ( O=>T_154, I2=>T_66, I1=>T_65, I0=>T_67 );
  GATE_T_155_I_1:   AND2 port map ( O=>T_155, I1=>H0_i_0_Q, I0=>H0_i_1_Q );
  GATE_T_156_I_1:   AND2 port map ( O=>T_156, I1=>H0_jumpup_7_Q, I0=>GATE_T_156_A );
  GATE_T_156_I_2:   INV port map ( O=>GATE_T_156_A, I0=>H0_i_3_Q );
  GATE_T_157_I_1:   AND2 port map ( O=>T_157, I1=>H0_i_0_Q, I0=>GATE_T_157_A );
  GATE_T_157_I_2:   INV port map ( O=>GATE_T_157_A, I0=>H0_i_1_Q );
  GATE_T_158_I_1:   AND2 port map ( O=>T_158, I1=>H0_jumpup_5_Q, I0=>GATE_T_158_A );
  GATE_T_158_I_2:   INV port map ( O=>GATE_T_158_A, I0=>H0_i_3_Q );
  GATE_T_159_I_1:   AND2 port map ( O=>T_159, I1=>H0_i_1_Q, I0=>GATE_T_159_A );
  GATE_T_159_I_2:   INV port map ( O=>GATE_T_159_A, I0=>H0_i_0_Q );
  GATE_T_160_I_1:   AND2 port map ( O=>T_160, I1=>H0_jumpup_6_Q, I0=>GATE_T_160_A );
  GATE_T_160_I_2:   INV port map ( O=>GATE_T_160_A, I0=>H0_i_3_Q );
  GATE_T_161_I_1:   NOR2 port map ( O=>T_161, I1=>H0_i_0_Q, I0=>H0_i_1_Q );
  GATE_T_162_I_1:   AND2 port map ( O=>T_162, I1=>H0_jumpup_4_Q, I0=>GATE_T_162_A );
  GATE_T_162_I_2:   INV port map ( O=>GATE_T_162_A, I0=>H0_i_3_Q );
  GATE_T_163_I_1:   AND2 port map ( O=>T_163, I1=>H0_i_0_Q, I0=>H0_i_1_Q );
  GATE_T_164_I_1:   AND2 port map ( O=>T_164, I1=>H0_jumpup_3_Q, I0=>GATE_T_164_A );
  GATE_T_164_I_2:   INV port map ( O=>GATE_T_164_A, I0=>H0_i_3_Q );
  GATE_T_165_I_1:   AND2 port map ( O=>T_165, I1=>H0_i_0_Q, I0=>GATE_T_165_A );
  GATE_T_165_I_2:   INV port map ( O=>GATE_T_165_A, I0=>H0_i_1_Q );
  GATE_T_166_I_1:   AND2 port map ( O=>T_166, I1=>H0_jumpup_1_Q, I0=>GATE_T_166_A );
  GATE_T_166_I_2:   INV port map ( O=>GATE_T_166_A, I0=>H0_i_3_Q );
  GATE_T_167_I_1:   AND2 port map ( O=>T_167, I1=>H0_i_1_Q, I0=>GATE_T_167_A );
  GATE_T_167_I_2:   INV port map ( O=>GATE_T_167_A, I0=>H0_i_0_Q );
  GATE_T_168_I_1:   AND2 port map ( O=>T_168, I1=>H0_jumpup_2_Q, I0=>GATE_T_168_A );
  GATE_T_168_I_2:   INV port map ( O=>GATE_T_168_A, I0=>H0_i_3_Q );
  GATE_T_169_I_1:   NOR2 port map ( O=>T_169, I1=>H0_i_0_Q, I0=>H0_i_1_Q );
  GATE_T_170_I_1:   AND2 port map ( O=>T_170, I1=>H0_jumpup_0_Q, I0=>GATE_T_170_A );
  GATE_T_170_I_2:   INV port map ( O=>GATE_T_170_A, I0=>H0_i_3_Q );

end NetList;