tcd1208_driver.vho

汽车四轮定位CCD驱动CPLD源代码

  signal GATE_T_164_A : std_logic;
  signal GATE_T_165_A : std_logic;
  signal GATE_T_166_A : std_logic;
  signal GATE_T_167_A : std_logic;
  signal GATE_T_168_A : std_logic;
  signal GATE_T_170_A : std_logic;

begin
  IN_dclk_I_1:   IBUF port map ( O=>dclk_PIN, I0=>dclk );
  IN_askdata_I_1:   IBUF port map ( O=>askdata_PIN, I0=>askdata );
  OUT_RS_I_1:   OBUF port map ( O=>RS, I0=>RS_Q );
  IN_clock_I_1:   IBUF port map ( O=>clock_PIN, I0=>clock );
  IN_CCDIN_I_1:   IBUF port map ( O=>CCDIN_PIN, I0=>CCDIN );
  IN_reset_I_1:   IBUF port map ( O=>reset_PIN, I0=>reset );
  OUT_O_I_1:   OBUF port map ( O=>O, I0=>O_COM );
  OUT_gout_I_1:   OBUF port map ( O=>gout, I0=>gout_Q );
  OUT_data1_I_1:   OBUF port map ( O=>data1, I0=>data1_Q );
  OUT_data2_I_1:   OBUF port map ( O=>data2, I0=>data2_Q );
  OUT_SH_I_1:   OBUF port map ( O=>SH, I0=>SH_Q );
  FF_RS_I_1:   DFFSH port map ( Q=>RS_Q, S=>reset_PIN, CLK=>clock_PIN, D=>RS_D );
  FF_gout_I_1:   DFF port map ( D=>gout_D, Q=>gout_Q, CLK=>P0_RSDFFRH_Q );
  FF_data1_I_1:   DFF port map ( D=>data1_D, Q=>data1_Q, CLK=>dclk_PIN );
  FF_data2_I_1:   DFF port map ( D=>data2_D, Q=>data2_Q, CLK=>dclk_PIN );
  FF_SH_I_1:   TFFSH port map ( Q=>SH_Q, S=>reset_PIN, CLK=>SH_C, T=>SH_T );
  FF_C0_GoutDFFRH_I_1:   DFFRH port map ( Q=>C0_GoutDFFRH_Q, R=>reset_PIN, CLK=>D0_GoutDFFRH_Q, D=>C0_GoutDFFRH_D );
  FF_D0_GoutDFFRH_I_1:   DFFRH port map ( Q=>D0_GoutDFFRH_Q, R=>reset_PIN, CLK=>P0_countc_0_Q, D=>D0_GoutDFFRH_D );
  FF_P0_countc_1_I_1:   DFFRH port map ( Q=>P0_countc_1_Q, R=>reset_PIN, CLK=>clock_PIN, D=>P0_countc_1_D );
  FF_P0_RSDFFRH_I_1:   DFFRH port map ( Q=>P0_RSDFFRH_Q, R=>reset_PIN, CLK=>clock_PIN, D=>P0_RSDFFRH_D );
  FF_P0_countc_0_I_1:   DFFRH port map ( Q=>P0_countc_0_Q, R=>reset_PIN, CLK=>clock_PIN, D=>P0_countc_0_D );
  FF_H0_countc_1_I_1:   DFFRH port map ( Q=>H0_countc_1_Q, R=>reset_PIN, CLK=>H0_countc_1_C, D=>H0_countc_1_D );
  FF_H0_countc_2_I_1:   DFFRH port map ( Q=>H0_countc_2_Q, R=>reset_PIN, CLK=>H0_countc_2_C, D=>H0_countc_2_D );
  FF_H0_countc_3_I_1:   DFFRH port map ( Q=>H0_countc_3_Q, R=>reset_PIN, CLK=>H0_countc_3_C, D=>H0_countc_3_D );
  FF_H0_countc_4_I_1:   DFFRH port map ( Q=>H0_countc_4_Q, R=>reset_PIN, CLK=>H0_countc_4_C, D=>H0_countc_4_D );
  FF_H0_countc_6_I_1:   TFFRH port map ( T=>H0_countc_6_T, Q=>H0_countc_6_Q, CLK=>H0_countc_6_C, R=>reset_PIN );
  FF_H0_countc_8_I_1:   TFFRH port map ( T=>H0_countc_8_T, Q=>H0_countc_8_Q, CLK=>H0_countc_8_C, R=>reset_PIN );
  FF_H0_countc_9_I_1:   TFFRH port map ( T=>H0_countc_9_T, Q=>H0_countc_9_Q, CLK=>H0_countc_9_C, R=>reset_PIN );
  FF_H0_countc_10_I_1:   TFFRH port map ( T=>H0_countc_10_T, Q=>H0_countc_10_Q, CLK=>H0_countc_10_C, R=>reset_PIN );
  FF_H0_jumpdown_0_I_1:   DFF port map ( D=>H0_jumpdown_0_D, Q=>H0_jumpdown_0_Q, CLK=>H0_jumpdown_0_C );
  FF_H0_jumpdown_1_I_1:   DFF port map ( D=>H0_jumpdown_1_D, Q=>H0_jumpdown_1_Q, CLK=>H0_jumpdown_1_C );
  FF_H0_jumpdown_2_I_1:   DFF port map ( D=>H0_jumpdown_2_D, Q=>H0_jumpdown_2_Q, CLK=>H0_jumpdown_2_C );
  FF_H0_jumpdown_3_I_1:   DFF port map ( D=>H0_jumpdown_3_D, Q=>H0_jumpdown_3_Q, CLK=>H0_jumpdown_3_C );
  FF_H0_jumpdown_4_I_1:   DFF port map ( D=>H0_jumpdown_4_D, Q=>H0_jumpdown_4_Q, CLK=>H0_jumpdown_4_C );
  FF_H0_jumpdown_5_I_1:   DFF port map ( D=>H0_jumpdown_5_D, Q=>H0_jumpdown_5_Q, CLK=>H0_jumpdown_5_C );
  FF_H0_jumpdown_6_I_1:   DFF port map ( D=>H0_jumpdown_6_D, Q=>H0_jumpdown_6_Q, CLK=>H0_jumpdown_6_C );
  FF_H0_jumpdown_7_I_1:   DFF port map ( D=>H0_jumpdown_7_D, Q=>H0_jumpdown_7_Q, CLK=>H0_jumpdown_7_C );
  FF_H0_jumpdown_8_I_1:   DFF port map ( D=>H0_jumpdown_8_D, Q=>H0_jumpdown_8_Q, CLK=>H0_jumpdown_8_C );
  FF_H0_jumpdown_9_I_1:   DFF port map ( D=>H0_jumpdown_9_D, Q=>H0_jumpdown_9_Q, CLK=>H0_jumpdown_9_C );
  FF_H0_jumpdown_10_I_1:   DFF port map ( D=>H0_jumpdown_10_D, Q=>H0_jumpdown_10_Q, CLK=>H0_jumpdown_10_C );
  FF_H0_jumpdown_11_I_1:   DFF port map ( D=>H0_jumpdown_11_D, Q=>H0_jumpdown_11_Q, CLK=>H0_jumpdown_11_C );
  FF_H0_countc_5_I_1:   TFFRH port map ( T=>H0_countc_5_T, Q=>H0_countc_5_Q, CLK=>H0_countc_5_C, R=>reset_PIN );
  FF_H0_countc_7_I_1:   TFFRH port map ( T=>H0_countc_7_T, Q=>H0_countc_7_Q, CLK=>H0_countc_7_C, R=>reset_PIN );
  FF_H0_countc_11_I_1:   TFFRH port map ( T=>H0_countc_11_T, Q=>H0_countc_11_Q, CLK=>H0_countc_11_C, R=>reset_PIN );
  FF_H0_jumpup_0_I_1:   DFF port map ( D=>H0_countc_0_Q, Q=>H0_jumpup_0_Q, CLK=>gout_Q );
  FF_H0_jumpup_1_I_1:   DFF port map ( D=>H0_countc_1_Q, Q=>H0_jumpup_1_Q, CLK=>gout_Q );
  FF_H0_jumpup_2_I_1:   DFF port map ( D=>H0_countc_2_Q, Q=>H0_jumpup_2_Q, CLK=>gout_Q );
  FF_H0_jumpup_3_I_1:   DFF port map ( D=>H0_countc_3_Q, Q=>H0_jumpup_3_Q, CLK=>gout_Q );
  FF_H0_jumpup_4_I_1:   DFF port map ( D=>H0_countc_4_Q, Q=>H0_jumpup_4_Q, CLK=>gout_Q );
  FF_H0_jumpup_5_I_1:   DFF port map ( D=>H0_countc_5_Q, Q=>H0_jumpup_5_Q, CLK=>gout_Q );
  FF_H0_jumpup_6_I_1:   DFF port map ( D=>H0_countc_6_Q, Q=>H0_jumpup_6_Q, CLK=>gout_Q );
  FF_H0_jumpup_7_I_1:   DFF port map ( D=>H0_countc_7_Q, Q=>H0_jumpup_7_Q, CLK=>gout_Q );
  FF_H0_jumpup_8_I_1:   DFF port map ( D=>H0_countc_8_Q, Q=>H0_jumpup_8_Q, CLK=>gout_Q );
  FF_H0_jumpup_9_I_1:   DFF port map ( D=>H0_countc_9_Q, Q=>H0_jumpup_9_Q, CLK=>gout_Q );
  FF_H0_jumpup_10_I_1:   DFF port map ( D=>H0_countc_10_Q, Q=>H0_jumpup_10_Q, CLK=>gout_Q );
  FF_H0_jumpup_11_I_1:   DFF port map ( D=>H0_countc_11_Q, Q=>H0_jumpup_11_Q, CLK=>gout_Q );
  FF_H0_i_3_I_1:   DFF port map ( D=>H0_i_3_D, Q=>H0_i_3_Q, CLK=>H0_i_3_C );
  FF_H0_i_1_I_1:   DFF port map ( D=>H0_i_1_D, Q=>H0_i_1_Q, CLK=>H0_i_1_C );
  FF_H0_i_0_I_1:   DFF port map ( D=>H0_i_0_D, Q=>H0_i_0_Q, CLK=>H0_i_0_C );
  FF_H0_countc_0_I_1:   DFFRH port map ( Q=>H0_countc_0_Q, R=>reset_PIN, CLK=>H0_countc_0_C, D=>H0_countc_0_D );
  FF_H0_i_2_I_1:   DFF port map ( D=>H0_i_2_D, Q=>H0_i_2_Q, CLK=>H0_i_2_C );
  FF_H0_LatchDFFRH_I_1:   TFFRH port map ( T=>H0_LatchDFFRH_T, Q=>H0_LatchDFFRH_Q, CLK=>H0_LatchDFFRH_C, R=>reset_PIN );
  GATE_T_0_I_1:   AND2 port map ( O=>T_0, I1=>P0_countc_0_Q, I0=>GATE_T_0_A );
  GATE_T_0_I_2:   INV port map ( O=>GATE_T_0_A, I0=>P0_countc_1_Q );
  GATE_O_I_1:   AND2 port map ( O=>O_COM, I1=>C0_GoutDFFRH_Q, I0=>GATE_O_A );
  GATE_O_I_2:   INV port map ( O=>GATE_O_A, I0=>H0_LatchDFFRH_Q );
  GATE_gout_D_I_1:   INV port map ( I0=>CCDIN_PIN, O=>gout_D );
  GATE_data1_D_I_1:   OR4 port map ( I0=>T_154, I1=>T_153, O=>data1_D, I2=>T_152, I3=>T_151 );
  GATE_data2_D_I_1:   OR4 port map ( I0=>T_134, I1=>T_133, O=>data2_D, I2=>T_132, I3=>T_131 );
  GATE_SH_T_I_1:   OR2 port map ( O=>SH_T, I1=>T_52, I0=>T_51 );
  GATE_SH_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>SH_C );
  GATE_C0_GoutDFFRH_D_I_1:   INV port map ( I0=>C0_GoutDFFRH_Q, O=>C0_GoutDFFRH_D );
  GATE_D0_GoutDFFRH_D_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>D0_GoutDFFRH_D );
  GATE_P0_countc_1_D_I_1:   XOR2 port map ( O=>P0_countc_1_D, I1=>P0_countc_0_Q, I0=>P0_countc_1_Q );
  GATE_P0_RSDFFRH_D_I_1:   AND2 port map ( O=>P0_RSDFFRH_D, I1=>P0_countc_0_Q, I0=>GATE_P0_RSDFFRH_D_A );
  GATE_P0_RSDFFRH_D_I_2:   INV port map ( O=>GATE_P0_RSDFFRH_D_A, I0=>P0_countc_1_Q );
  GATE_P0_countc_0_D_I_1:   INV port map ( I0=>P0_countc_0_Q, O=>P0_countc_0_D );
  GATE_H0_countc_1_D_I_1:   XOR2 port map ( O=>H0_countc_1_D, I1=>H0_countc_0_Q, I0=>H0_countc_1_Q );
  GATE_H0_countc_1_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_1_C );
  GATE_H0_countc_2_D_I_1:   OR3 port map ( O=>H0_countc_2_D, I2=>T_49, I1=>T_48, I0=>T_50 );
  GATE_H0_countc_2_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_2_C );
  GATE_T_1_I_1:   OR3 port map ( O=>T_1, I2=>T_120, I1=>T_47, I0=>T_119 );
  GATE_H0_countc_3_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_3_C );
  GATE_H0_countc_4_D_X1_I_1:   AND4 port map ( O=>H0_countc_4_D_X1, I3=>H0_countc_0_Q, I2=>H0_countc_3_Q, I1=>H0_countc_2_Q, I0=>H0_countc_1_Q );
  GATE_H0_countc_4_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_4_C );
  GATE_H0_countc_6_T_I_1:   AND3 port map ( O=>H0_countc_6_T, I2=>T_117, I1=>T_118, I0=>T_116 );
  GATE_H0_countc_6_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_6_C );
  GATE_H0_countc_8_T_I_1:   AND4 port map ( O=>H0_countc_8_T, I3=>T_112, I2=>T_113, I1=>T_114, I0=>T_115 );
  GATE_H0_countc_8_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_8_C );
  GATE_H0_countc_9_T_I_1:   AND3 port map ( O=>H0_countc_9_T, I2=>T_110, I1=>T_111, I0=>T_109 );
  GATE_H0_countc_9_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_9_C );
  GATE_H0_countc_10_T_I_1:   AND4 port map ( O=>H0_countc_10_T, I3=>T_106, I2=>T_107, I1=>T_108, I0=>H0_countc_0_Q );
  GATE_H0_countc_10_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_10_C );
  GATE_H0_jumpdown_0_D_I_1:   OR2 port map ( O=>H0_jumpdown_0_D, I1=>T_42, I0=>T_41 );
  GATE_H0_jumpdown_0_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_0_C );
  GATE_H0_jumpdown_1_D_I_1:   OR2 port map ( O=>H0_jumpdown_1_D, I1=>T_40, I0=>T_39 );
  GATE_H0_jumpdown_1_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_1_C );
  GATE_H0_jumpdown_2_D_I_1:   OR2 port map ( O=>H0_jumpdown_2_D, I1=>T_38, I0=>T_37 );
  GATE_H0_jumpdown_2_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_2_C );
  GATE_H0_jumpdown_3_D_I_1:   OR2 port map ( O=>H0_jumpdown_3_D, I1=>T_36, I0=>T_35 );
  GATE_H0_jumpdown_3_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_3_C );
  GATE_H0_jumpdown_4_D_I_1:   OR2 port map ( O=>H0_jumpdown_4_D, I1=>T_34, I0=>T_33 );
  GATE_H0_jumpdown_4_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_4_C );
  GATE_H0_jumpdown_5_D_I_1:   OR2 port map ( O=>H0_jumpdown_5_D, I1=>T_32, I0=>T_31 );
  GATE_H0_jumpdown_5_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_5_C );
  GATE_H0_jumpdown_6_D_I_1:   OR2 port map ( O=>H0_jumpdown_6_D, I1=>T_30, I0=>T_29 );
  GATE_H0_jumpdown_6_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_6_C );
  GATE_H0_jumpdown_7_D_I_1:   OR2 port map ( O=>H0_jumpdown_7_D, I1=>T_28, I0=>T_27 );
  GATE_H0_jumpdown_7_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_7_C );
  GATE_H0_jumpdown_8_D_I_1:   OR2 port map ( O=>H0_jumpdown_8_D, I1=>T_26, I0=>T_25 );
  GATE_H0_jumpdown_8_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_8_C );
  GATE_H0_jumpdown_9_D_I_1:   OR2 port map ( O=>H0_jumpdown_9_D, I1=>T_24, I0=>T_23 );
  GATE_H0_jumpdown_9_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_9_C );
  GATE_H0_jumpdown_10_D_I_1:   OR2 port map ( O=>H0_jumpdown_10_D, I1=>T_22, I0=>T_21 );
  GATE_H0_jumpdown_10_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_10_C );
  GATE_H0_jumpdown_11_D_I_1:   OR2 port map ( O=>H0_jumpdown_11_D, I1=>T_20, I0=>T_19 );
  GATE_H0_jumpdown_11_C_I_1:   INV port map ( I0=>gout_Q, O=>H0_jumpdown_11_C );
  GATE_H0_countc_5_T_I_1:   OR2 port map ( O=>H0_countc_5_T, I1=>T_18, I0=>T_17 );
  GATE_H0_countc_5_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_5_C );
  GATE_H0_countc_7_T_I_1:   OR2 port map ( O=>H0_countc_7_T, I1=>T_16, I0=>T_15 );
  GATE_H0_countc_7_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_7_C );
  GATE_H0_countc_11_T_I_1:   OR2 port map ( O=>H0_countc_11_T, I1=>T_14, I0=>T_13 );
  GATE_H0_countc_11_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_11_C );
  GATE_H0_i_3_D_I_1:   OR2 port map ( O=>H0_i_3_D, I1=>T_12, I0=>T_11 );
  GATE_H0_i_3_C_I_1:   INV port map ( I0=>dclk_PIN, O=>H0_i_3_C );
  GATE_H0_i_1_D_I_1:   OR2 port map ( O=>H0_i_1_D, I1=>T_10, I0=>T_9 );
  GATE_H0_i_1_C_I_1:   INV port map ( I0=>dclk_PIN, O=>H0_i_1_C );
  GATE_H0_i_0_D_I_1:   OR2 port map ( O=>H0_i_0_D, I1=>T_8, I0=>T_7 );
  GATE_H0_i_0_C_I_1:   INV port map ( I0=>dclk_PIN, O=>H0_i_0_C );
  GATE_H0_countc_0_D_I_1:   INV port map ( I0=>H0_countc_0_Q, O=>H0_countc_0_D );
  GATE_H0_countc_0_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_countc_0_C );
  GATE_H0_i_2_D_I_1:   OR3 port map ( O=>H0_i_2_D, I2=>T_5, I1=>T_4, I0=>T_6 );
  GATE_H0_i_2_C_I_1:   INV port map ( I0=>dclk_PIN, O=>H0_i_2_C );
  GATE_H0_LatchDFFRH_T_I_1:   OR2 port map ( O=>H0_LatchDFFRH_T, I1=>T_3, I0=>T_2 );
  GATE_H0_LatchDFFRH_C_I_1:   INV port map ( I0=>D0_GoutDFFRH_Q, O=>H0_LatchDFFRH_C );
  GATE_H0_countc_4_D_I_1:   XOR2 port map ( O=>H0_countc_4_D, I1=>H0_countc_4_D_X1, I0=>H0_countc_4_Q );
  GATE_RS_D_I_1:   INV port map ( I0=>T_0, O=>RS_D );
  GATE_H0_countc_3_D_I_1:   INV port map ( I0=>T_1, O=>H0_countc_3_D );
  GATE_T_2_I_1:   AND4 port map ( O=>T_2, I3=>T_80, I2=>T_81, I1=>T_82, I0=>GATE_T_2_A );
  GATE_T_2_I_2:   INV port map ( I0=>H0_LatchDFFRH_Q, O=>GATE_T_2_A );
  GATE_T_3_I_1:   AND4 port map ( O=>T_3, I3=>T_77, I2=>T_78, I1=>T_79, I0=>H0_LatchDFFRH_Q );
  GATE_T_4_I_1:   AND4 port map ( O=>T_4, I3=>H0_i_1_Q, I2=>askdata_PIN, I1=>H0_i_0_Q, I0=>GATE_T_4_A );
  GATE_T_4_I_2:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_4_A );
  GATE_T_5_I_3:   AND4 port map ( O=>T_5, I3=>H0_i_2_Q, I2=>askdata_PIN, I1=>GATE_T_5_B, I0=>GATE_T_5_A );
  GATE_T_5_I_2:   INV port map ( I0=>H0_i_0_Q, O=>GATE_T_5_B );
  GATE_T_5_I_1:   INV port map ( I0=>H0_i_3_Q, O=>GATE_T_5_A );
  GATE_T_6_I_3:   AND4 port map ( O=>T_6, I3=>H0_i_2_Q, I2=>askdata_PIN, I1=>GATE_T_6_B, I0=>GATE_T_6_A );
  GATE_T_6_I_2:   INV port map ( I0=>H0_i_1_Q, O=>GATE_T_6_B );
  GATE_T_6_I_1:   INV port map ( I0=>H0_i_3_Q, O=>GATE_T_6_A );
  GATE_T_7_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_7_A );
  GATE_T_7_I_2:   INV port map ( I0=>H0_i_0_Q, O=>GATE_T_7_B );
  GATE_T_7_I_3:   AND3 port map ( O=>T_7, I0=>askdata_PIN, I2=>GATE_T_7_A, I1=>GATE_T_7_B );
  GATE_T_8_I_1:   INV port map ( I0=>H0_i_0_Q, O=>GATE_T_8_A );
  GATE_T_8_I_2:   INV port map ( I0=>H0_i_3_Q, O=>GATE_T_8_B );
  GATE_T_8_I_3:   AND3 port map ( O=>T_8, I0=>askdata_PIN, I2=>GATE_T_8_A, I1=>GATE_T_8_B );
  GATE_T_9_I_1:   INV port map ( I0=>H0_i_0_Q, O=>GATE_T_9_A );
  GATE_T_9_I_2:   AND3 port map ( O=>T_9, I2=>H0_i_1_Q, I1=>askdata_PIN, I0=>GATE_T_9_A );
  GATE_T_10_I_1:   INV port map ( I0=>H0_i_1_Q, O=>GATE_T_10_A );
  GATE_T_10_I_2:   AND3 port map ( O=>T_10, I2=>askdata_PIN, I1=>H0_i_0_Q, I0=>GATE_T_10_A );
  GATE_T_11_I_1:   AND3 port map ( O=>T_11, I2=>T_84, I1=>H0_i_2_Q, I0=>T_83 );
  GATE_T_12_I_1:   INV port map ( I0=>H0_i_2_Q, O=>GATE_T_12_A );
  GATE_T_12_I_2:   AND3 port map ( O=>T_12, I2=>H0_i_3_Q, I1=>askdata_PIN, I0=>GATE_T_12_A );
  GATE_T_13_I_1:   AND4 port map ( O=>T_13, I3=>T_89, I2=>T_90, I1=>T_91, I0=>T_92 );
  GATE_T_14_I_1:   AND4 port map ( O=>T_14, I3=>T_85, I2=>T_86, I1=>T_87, I0=>T_88 );
  GATE_T_15_I_1:   AND4 port map ( O=>T_15, I3=>T_96, I2=>T_97, I1=>T_98, I0=>T_99 );
  GATE_T_16_I_1:   AND4 port map ( O=>T_16, I3=>T_93, I2=>T_94, I1=>T_95, I0=>H0_countc_0_Q );
  GATE_T_17_I_1:   AND4 port map ( O=>T_17, I3=>T_102, I2=>T_103, I1=>T_104, I0=>T_105 );
  GATE_T_18_I_1:   AND3 port map ( O=>T_18, I2=>T_101, I1=>H0_countc_0_Q, I0=>T_100 );
  GATE_T_19_I_1:   AND2 port map ( O=>T_19, I1=>H0_countc_11_Q, I0=>askdata_PIN );
  GATE_T_20_I_1:   AND2 port map ( O=>T_20, I1=>H0_jumpdown_11_Q, I0=>GATE_T_20_A );
  GATE_T_20_I_2:   INV port map ( O=>GATE_T_20_A, I0=>askdata_PIN );
  GATE_T_21_I_1:   AND2 port map ( O=>T_21, I1=>H0_jumpdown_10_Q, I0=>GATE_T_21_A );
  GATE_T_21_I_2:   INV port map ( O=>GATE_T_21_A, I0=>askdata_PIN );
  GATE_T_22_I_1:   AND2 port map ( O=>T_22, I1=>H0_countc_10_Q, I0=>askdata_PIN );
  GATE_T_23_I_1:   AND2 port map ( O=>T_23, I1=>H0_jumpdown_9_Q, I0=>GATE_T_23_A );
  GATE_T_23_I_2:   INV port map ( O=>GATE_T_23_A, I0=>askdata_PIN );
  GATE_T_24_I_1:   AND2 port map ( O=>T_24, I1=>H0_countc_9_Q, I0=>askdata_PIN );
  GATE_T_25_I_1:   AND2 port map ( O=>T_25, I1=>H0_jumpdown_8_Q, I0=>GATE_T_25_A );
  GATE_T_25_I_2:   INV port map ( O=>GATE_T_25_A, I0=>askdata_PIN );
  GATE_T_26_I_1:   AND2 port map ( O=>T_26, I1=>H0_countc_8_Q, I0=>askdata_PIN );
  GATE_T_27_I_1:   AND2 port map ( O=>T_27, I1=>H0_countc_7_Q, I0=>askdata_PIN );
  GATE_T_28_I_1:   AND2 port map ( O=>T_28, I1=>H0_jumpdown_7_Q, I0=>GATE_T_28_A );
  GATE_T_28_I_2:   INV port map ( O=>GATE_T_28_A, I0=>askdata_PIN );
  GATE_T_29_I_1:   AND2 port map ( O=>T_29, I1=>H0_jumpdown_6_Q, I0=>GATE_T_29_A );
  GATE_T_29_I_2:   INV port map ( O=>GATE_T_29_A, I0=>askdata_PIN );
  GATE_T_30_I_1:   AND2 port map ( O=>T_30, I1=>H0_countc_6_Q, I0=>askdata_PIN );
  GATE_T_31_I_1:   AND2 port map ( O=>T_31, I1=>H0_countc_5_Q, I0=>askdata_PIN );
  GATE_T_32_I_1:   AND2 port map ( O=>T_32, I1=>H0_jumpdown_5_Q, I0=>GATE_T_32_A );
  GATE_T_32_I_2:   INV port map ( O=>GATE_T_32_A, I0=>askdata_PIN );
  GATE_T_33_I_1:   AND2 port map ( O=>T_33, I1=>H0_jumpdown_4_Q, I0=>GATE_T_33_A );
  GATE_T_33_I_2:   INV port map ( O=>GATE_T_33_A, I0=>askdata_PIN );
  GATE_T_34_I_1:   AND2 port map ( O=>T_34, I1=>H0_countc_4_Q, I0=>askdata_PIN );
  GATE_T_35_I_1:   AND2 port map ( O=>T_35, I1=>H0_jumpdown_3_Q, I0=>GATE_T_35_A );
  GATE_T_35_I_2:   INV port map ( O=>GATE_T_35_A, I0=>askdata_PIN );
  GATE_T_36_I_1:   AND2 port map ( O=>T_36, I1=>H0_countc_3_Q, I0=>askdata_PIN );