📄 ddoor.vm
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//
// Written by Synplify
// Sat Apr 19 17:35:54 2003
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\d:\isptools\synpbase\lib\vhd\std.vhd "
// file 2 "\e:\tcd-1208\2003.4.19\ddoor.vhd "
// file 3 "\d:\isptools\synpbase\lib\vhd\std1164.vhd "
`timescale 100 ps/100 ps
module IBUF (
O,
I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
assign #(1) O = I0;
assign true = 1'b1;
assign false = 1'b0;
endmodule /* IBUF */
module MACH_DFF (
Q,
D,
CLK,
R,
S,
NOTIFIER
);
output Q;
input D;
input CLK;
input R;
input S;
input NOTIFIER;
wire Q ;
wire D ;
wire CLK ;
wire R ;
wire S ;
wire NOTIFIER ;
wire un0 ;
wire un1 ;
wire true ;
wire false ;
assign #(1) un0 = ~ S;
assign #(1) un1 = ~ R;
assign true = 1'b1;
assign false = 1'b0;
reg r_e_g0; // dffrs
always @(posedge CLK or posedge un1 or posedge un0 )
r_e_g0 = #1 un1 ? 1'b0 : (un0 ? 1'b1 : D );
assign Q = r_e_g0;
endmodule /* MACH_DFF */
module DFF (
Q,
D,
CLK
);
output Q;
input D;
input CLK;
wire Q ;
wire D ;
wire CLK ;
wire un0 ;
wire true ;
wire notifier ;
wire false ;
MACH_DFF INS4 (
.Q(un0),
.D(D),
.CLK(CLK),
.R(true),
.S(true),
.NOTIFIER(notifier)
);
assign true = 1'b1;
assign false = 1'b0;
assign notifier = 1'b0;
assign Q = un0;
endmodule /* DFF */
module OBUF (
O,
I0
);
output O;
input I0;
wire O ;
wire I0 ;
wire true ;
wire false ;
assign #(1) O = I0;
assign true = 1'b1;
assign false = 1'b0;
endmodule /* OBUF */
module Ddoor (
ctrl,
Gin,
Gout
);
input ctrl;
input Gin;
output Gout;
wire ctrl ;
wire Gin ;
wire Gout ;
wire ctrl_c ;
wire Gin_c ;
wire Gout_c ;
wire GND ;
wire VCC ;
IBUF ctrl_Z (
.O(ctrl_c),
.I0(ctrl)
);
IBUF Gin_Z (
.O(Gin_c),
.I0(Gin)
);
// @2:16
DFF GoutDFF (
.Q(Gout_c),
.D(Gin_c),
.CLK(ctrl_c)
);
OBUF Gout_Z (
.O(Gout),
.I0(Gout_c)
);
assign GND = 1'b0;
assign VCC = 1'b1;
endmodule /* Ddoor */
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