counter2.vhm

汽车四轮定位CCD驱动CPLD源代码

--
-- Written by Synplicity
-- Sat Apr 19 17:36:03 2003
--

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity MACH_DFF is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  R :  in std_logic;
  S :  in std_logic;
  NOTIFIER :  in std_logic);
end MACH_DFF;

architecture beh of MACH_DFF is
  signal UN0 : std_logic ;
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  UN0 <= not S;
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  II_Q: prim_dff port map (Q, D, CLK, UN1, UN0);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity DFFRH is
port(
  Q :  out std_logic;
  D :  in std_logic;
  CLK :  in std_logic;
  R :  in std_logic);
end DFFRH;

architecture beh of DFFRH is
  signal UN1 : std_logic ;
  signal NN_1 : std_logic ;
  signal NOTIFIER : std_logic ;
  signal NN_2 : std_logic ;
  component MACH_DFF
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic;
    S :  in std_logic;
    NOTIFIER :  in std_logic  );
  end component;
begin
  II_INS1: MACH_DFF port map (
    Q => Q,
    D => D,
    CLK => CLK,
    R => UN1,
    S => NN_1,
    NOTIFIER => NOTIFIER);
  UN1 <= not R;
  NN_1 <= '1';
  NN_2 <= '0';
  NOTIFIER <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity IBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end IBUF;

architecture beh of IBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity INV is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end INV;

architecture beh of INV is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= not I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity OBUF is
port(
  O :  out std_logic;
  I0 :  in std_logic);
end OBUF;

architecture beh of OBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I0;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
library synplify;
use synplify.components.all;
entity counter2 is
port(
  clk :  in std_logic;
  reset :  in std_logic;
  Gout :  out std_logic);
end counter2;

architecture beh of counter2 is
  signal GOUT_I : std_logic ;
  signal CLK_C : std_logic ;
  signal RESET_C : std_logic ;
  signal GOUT_C : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component IBUF
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component DFFRH
    port(Q :  out std_logic;
    D :  in std_logic;
    CLK :  in std_logic;
    R :  in std_logic  );
  end component;
  component OBUF
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
  component INV
    port(O :  out std_logic;
    I0 :  in std_logic  );
  end component;
begin
  II_CLK: IBUF port map (
    O => CLK_C,
    I0 => clk);
  II_RESET: IBUF port map (
    O => RESET_C,
    I0 => reset);
  II_GOUTDFFRH: DFFRH port map (
    Q => GOUT_C,
    D => GOUT_I,
    CLK => CLK_C,
    R => RESET_C);
  II_GOUT: OBUF port map (
    O => Gout,
    I0 => GOUT_C);
  II_GOUT_I: INV port map (
    O => GOUT_I,
    I0 => GOUT_C);
  GND <= '0';
  VCC <= '1';
end beh;