top.vhd

汽车四轮定位CCD驱动CPLD源代码

-- VHDL model created from schematic top.sch -- Apr 19 17:36:39 2003

LIBRARY vanmacro;
USE vanmacro.components.ALL;
LIBRARY ieee;
LIBRARY generics;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
USE generics.components.ALL;

entity TOP is
      Port ( askdata : In    std_logic;
               CCDIN : In    std_logic;
               clock : In    std_logic;
                dclk : In    std_logic;
               reset : In    std_logic;
               data1 : Out   std_logic;
               data2 : Out   std_logic;
                gout : Out   std_logic;
                   O : Out   std_logic;
                  RS : Out   std_logic;
                  SH : Out   std_logic );
end TOP;

architecture SCHEMATIC of TOP is

   SIGNAL gnd : std_logic := '0';
   SIGNAL vcc : std_logic := '1';

   signal     N_59 : std_logic;
   signal     N_60 : std_logic;
   signal     N_58 : std_logic;
   signal     N_54 : std_logic;
   signal     N_48 : std_logic;
   signal     N_34 : std_logic;
   signal     N_27 : std_logic;
   signal     N_22 : std_logic;

   component DDOOR
      Port (    ctrl : In    std_logic;
                 Gin : In    std_logic;
                Gout : Out   std_logic );
   end component;

   component COUNTER2PLUS
      Port (     clk : In    std_logic;
               reset : In    std_logic;
                Gout : Out   std_logic;
                  RS : Out   std_logic );
   end component;

   component DRIVER
      Port ( askdata : In    std_logic;
               ccdin : In    std_logic;
                 clk : In    std_logic;
             dataclk : In    std_logic;
               reset : In    std_logic;
               data1 : Out   std_logic;
               data2 : Out   std_logic;
               Latch : Out   std_logic;
                  SH : Out   std_logic );
   end component;

   component COUNTER2
      Port (     clk : In    std_logic;
               reset : In    std_logic;
                Gout : Out   std_logic );
   end component;

begin

   I16 : G_BUF
      Port Map ( A=>N_59, Y=>gout );
   I13 : DDOOR
      Port Map ( ctrl=>N_34, Gin=>N_54, Gout=>N_59 );
   I12 : COUNTER2PLUS
      Port Map ( clk=>N_22, reset=>reset, Gout=>N_27, RS=>N_34 );
   I15 : G_INV
      Port Map ( A=>CCDIN, YN=>N_54 );
   I11 : G_INV
      Port Map ( A=>N_34, YN=>RS );
   I8 : DRIVER
      Port Map ( askdata=>askdata, ccdin=>N_59, clk=>N_60, dataclk=>dclk,
                 reset=>reset, data1=>data1, data2=>data2, Latch=>N_58,
                 SH=>SH );
   I6 : G_2AND1
      Port Map ( AN=>N_58, B=>N_48, Y=>O );
   I2 : G_CLKBUF
      Port Map ( I=>clock, O=>N_22 );
   I3 : COUNTER2
      Port Map ( clk=>N_60, reset=>reset, Gout=>N_48 );
   I4 : COUNTER2
      Port Map ( clk=>N_27, reset=>reset, Gout=>N_60 );

end SCHEMATIC;