top.bl0

汽车四轮定位CCD驱动CPLD源代码

#$ TOOL ispDesignEXPERT 8.3.02.12
#$ DATE Sun Apr 20 16:05:21 2003
#$ TITLE top.bls 
#$ MODULE top
#$ PINS 15 addr1 addr0 addr2 addr3 data1 data2 gout'o'  dclk askdata RS'o'  clock CCDIN reset SH \
#  O'o' 
#$ NODES 17 N_59'o'  N_60'o'  N_61'o'  N_62'o'  N_63'o'  N_64'o'  N_54 N_55'o'  N_56 N_57 N_58 N_49 N_53'o'  N_48 \
#  N_34 N_27 N_22'o' 
#$ INTERFACE counter2  3 clk'i'  reset'i'  Gout'o' 
#$ INTERFACE counter2plus  4 clk'i'  reset'i'  Gout'o'  RS'o' 
#$ INTERFACE ddoor  3 Gin'i'  ctrl'i'  Gout'o' 
#$ INTERFACE driver  14 addr0'i'  addr1'i'  addr2'i'  addr3'i'  askdata'i'  ccdin'i'  clk'i'  dataclk'i'  reset'i'  Efficiant'o'  \
#  Latch'o'  SH'o'  data1'o'  data2'o' 
#$ INSTANCE I3 counter2 3 N_56 reset N_48
#$ INSTANCE I4 counter2 3 N_27 reset N_56
#$ INSTANCE I12 counter2plus 4 N_22 reset N_27 N_34
#$ INSTANCE I13 ddoor 3 N_53 N_34 N_57
#$ INSTANCE I17 ddoor 3 N_55 N_56 N_54
#$ INSTANCE I8 driver 14 N_62 N_61 N_60 N_59 N_64 N_54 N_56 N_63 reset N_58 N_49 SH data1 \
#  data2
.model top
.inputs N_57.BLIF N_58.BLIF N_49.BLIF N_48.BLIF N_54.BLIF addr3.BLIF \
addr2.BLIF addr1.BLIF addr0.BLIF dclk.BLIF askdata.BLIF clock.BLIF N_34.BLIF \
CCDIN.BLIF
.outputs N_55 O gout N_59 N_60 N_61 N_62 N_63 N_64 N_22 RS N_53

.subckt g_2and A.BLIF=N_57.BLIF B.BLIF=N_58.BLIF Y=N_55

.subckt g_2and1 AN.BLIF=N_49.BLIF B.BLIF=N_48.BLIF Y=O

.subckt g_buf A.BLIF=N_54.BLIF Y=gout

.subckt g_buf A.BLIF=addr3.BLIF Y=N_59

.subckt g_buf A.BLIF=addr2.BLIF Y=N_60

.subckt g_buf A.BLIF=addr1.BLIF Y=N_61

.subckt g_buf A.BLIF=addr0.BLIF Y=N_62

.subckt g_buf A.BLIF=dclk.BLIF Y=N_63

.subckt g_buf A.BLIF=askdata.BLIF Y=N_64

.subckt g_clkbuf I.BLIF=clock.BLIF O=N_22

.subckt g_inv A.BLIF=N_34.BLIF YN=RS

.subckt g_inv A.BLIF=CCDIN.BLIF YN=N_53
.end
.model g_2and
.inputs A.BLIF B.BLIF
.outputs Y
.names A.BLIF B.BLIF Y
11 1
0- 0
-0 0
.end
.model g_2and1
.inputs AN.BLIF B.BLIF
.outputs Y
.names AN.BLIF B.BLIF Y
01 1
1- 0
-0 0
.end
.model g_buf
.inputs A.BLIF
.outputs Y
.names A.BLIF Y
1 1
0 0
.end
.model g_clkbuf
.inputs I.BLIF
.outputs O
.names I.BLIF O
1 1
0 0
.end
.model g_inv
.inputs A.BLIF
.outputs YN
.names A.BLIF YN
0 1
1 0
.end