📄 tcd1208_driver.sdf

📁 汽车四轮定位CCD驱动CPLD源代码
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    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_5_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_6_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_7_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_8_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_9_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_10_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_11_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "TFFRH")
    (INSTANCE FF_H0_countc_5_I_1)
    (DELAY
      (ABSOLUTE
        (PORT T (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP T (posedge CLK) (50:50:50))
        (HOLD T (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "TFFRH")
    (INSTANCE FF_H0_countc_7_I_1)
    (DELAY
      (ABSOLUTE
        (PORT T (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP T (posedge CLK) (50:50:50))
        (HOLD T (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "TFFRH")
    (INSTANCE FF_H0_countc_11_I_1)
    (DELAY
      (ABSOLUTE
        (PORT T (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP T (posedge CLK) (50:50:50))
        (HOLD T (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_0_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_1_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_2_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_3_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_4_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_5_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_6_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_7_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_8_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_9_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_10_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpup_11_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_i_3_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_i_1_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_i_0_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_H0_countc_0_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_i_2_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "TFFRH")
    (INSTANCE FF_H0_LatchDFFRH_I_1)
    (DELAY
      (ABSOLUTE
        (PORT T (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP T (posedge CLK) (50:50:50))
        (HOLD T (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "AND2")
    (INSTANCE GATE_O_I_1)
    (DELAY
      (ABSOLUTE
        (PORT I0 (0:0:0) (0:0:0) )
        (PORT I1 (0:0:0) (0:0:0) )
        (IOPATH I0 O (70:70:70) (70:70:70) )
        (IOPATH I1 O (70:70:70) (70:70:70) )
      )
    )
  )
)
上一页 12
💿 文件大小 196 K
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