tcd1208_driver.sdf

汽车四轮定位CCD驱动CPLD源代码

// SDF delay-file
(DELAYFILE
  (SDFVERSION "2.1")
  (DESIGN "tcd1208_driver")
  (DATE "4/19/2003 17:36:40")
  (VENDOR "Lattice Semiconductor")
  (PROGRAM "SDF Generator")
  (VERSION "8.3.02.12_DE_ADV_PC Data sheet version: RevD-8/2000")
  (DIVIDER /)
  (VOLTAGE :5.0:)
  (PROCESS "typical")
  (TEMPERATURE :25:)
  (TIMESCALE 100ps)
  (CELL
    (CELLTYPE "OBUF")
    (INSTANCE OUT_RS_I_1)
    (DELAY
      (ABSOLUTE
        (IOPATH I0 O (30:30:30) (30:30:30) )
      )
    )
  )
  (CELL
    (CELLTYPE "OBUF")
    (INSTANCE OUT_O_I_1)
    (DELAY
      (ABSOLUTE
        (IOPATH I0 O (30:30:30) (30:30:30) )
      )
    )
  )
  (CELL
    (CELLTYPE "OBUF")
    (INSTANCE OUT_gout_I_1)
    (DELAY
      (ABSOLUTE
        (IOPATH I0 O (30:30:30) (30:30:30) )
      )
    )
  )
  (CELL
    (CELLTYPE "OBUF")
    (INSTANCE OUT_data1_I_1)
    (DELAY
      (ABSOLUTE
        (IOPATH I0 O (30:30:30) (30:30:30) )
      )
    )
  )
  (CELL
    (CELLTYPE "OBUF")
    (INSTANCE OUT_data2_I_1)
    (DELAY
      (ABSOLUTE
        (IOPATH I0 O (30:30:30) (30:30:30) )
      )
    )
  )
  (CELL
    (CELLTYPE "OBUF")
    (INSTANCE OUT_SH_I_1)
    (DELAY
      (ABSOLUTE
        (IOPATH I0 O (30:30:30) (30:30:30) )
      )
    )
  )
  (CELL
    (CELLTYPE "DFFSH")
    (INSTANCE FF_RS_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT S (0:0:0) (0:0:0) )
        (IOPATH CLK Q (30:30:30) (30:30:30) )
        (IOPATH S Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (55:55:55))
        (HOLD D (posedge CLK) (0:0:0))
        (RECOVERY (negedge S) (posedge CLK) (80:80:80))
        (WIDTH (posedge S) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_gout_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_data1_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_data2_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "TFFSH")
    (INSTANCE FF_SH_I_1)
    (DELAY
      (ABSOLUTE
        (PORT T (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT S (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH S Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP T (posedge CLK) (50:50:50))
        (HOLD T (posedge CLK) (40:40:40))
        (RECOVERY (negedge S) (posedge CLK) (80:80:80))
        (WIDTH (posedge S) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_C0_GoutDFFRH_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_D0_GoutDFFRH_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_P0_countc_1_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (30:30:30) (30:30:30) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (55:55:55))
        (HOLD D (posedge CLK) (0:0:0))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_P0_RSDFFRH_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (30:30:30) (30:30:30) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (55:55:55))
        (HOLD D (posedge CLK) (0:0:0))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_P0_countc_0_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (30:30:30) (30:30:30) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (55:55:55))
        (HOLD D (posedge CLK) (0:0:0))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_H0_countc_1_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_H0_countc_2_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_H0_countc_3_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFFRH")
    (INSTANCE FF_H0_countc_4_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "TFFRH")
    (INSTANCE FF_H0_countc_6_I_1)
    (DELAY
      (ABSOLUTE
        (PORT T (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP T (posedge CLK) (50:50:50))
        (HOLD T (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "TFFRH")
    (INSTANCE FF_H0_countc_8_I_1)
    (DELAY
      (ABSOLUTE
        (PORT T (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP T (posedge CLK) (50:50:50))
        (HOLD T (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "TFFRH")
    (INSTANCE FF_H0_countc_9_I_1)
    (DELAY
      (ABSOLUTE
        (PORT T (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP T (posedge CLK) (50:50:50))
        (HOLD T (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "TFFRH")
    (INSTANCE FF_H0_countc_10_I_1)
    (DELAY
      (ABSOLUTE
        (PORT T (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (PORT R (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
        (IOPATH R Q (110:110:110) (110:110:110) )
      )
    )
    (TIMINGCHECK
        (SETUP T (posedge CLK) (50:50:50))
        (HOLD T (posedge CLK) (40:40:40))
        (RECOVERY (negedge R) (posedge CLK) (80:80:80))
        (WIDTH (posedge R) (100:100:100))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_0_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_1_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_2_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_3_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )
    (TIMINGCHECK
        (SETUP D (posedge CLK) (40:40:40))
        (HOLD D (posedge CLK) (40:40:40))
        (WIDTH (posedge CLK) (50:50:50))
    )
  )
  (CELL
    (CELLTYPE "DFF")
    (INSTANCE FF_H0_jumpdown_4_I_1)
    (DELAY
      (ABSOLUTE
        (PORT D (0:0:0) (0:0:0) )
        (PORT CLK (0:0:0) (0:0:0) )
        (IOPATH CLK Q (80:80:80) (80:80:80) )
      )
    )