nco.map.rpt

使用QUARTUS 2编译的DDS的源码

; IGNORE_CARRY_BUFFERS   ; OFF         ; IGNORE_CARRY                                ;
; AUTO_CASCADE_CHAINS    ; ON          ; AUTO_CASCADE                                ;
; IGNORE_CASCADE_BUFFERS ; OFF         ; IGNORE_CASCADE                              ;
+------------------------+-------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component ;
+------------------------+------------------------------------+------------------------------------------+
; Parameter Name         ; Value                              ; Type                                     ;
+------------------------+------------------------------------+------------------------------------------+
; LPM_WIDTH              ; 7                                  ; Integer                                  ;
; LPM_WIDTHAD            ; 6                                  ; Integer                                  ;
; LPM_NUMWORDS           ; 64                                 ; Untyped                                  ;
; LPM_ADDRESS_CONTROL    ; REGISTERED                         ; Untyped                                  ;
; LPM_OUTDATA            ; UNREGISTERED                       ; Untyped                                  ;
; LPM_FILE               ; G:\\test\\quartus\\NCO\\ncosin.mif ; Untyped                                  ;
; DEVICE_FAMILY          ; Stratix                            ; Untyped                                  ;
; AUTO_CARRY_CHAINS      ; ON                                 ; AUTO_CARRY                               ;
; IGNORE_CARRY_BUFFERS   ; OFF                                ; IGNORE_CARRY                             ;
; AUTO_CASCADE_CHAINS    ; ON                                 ; AUTO_CASCADE                             ;
; IGNORE_CASCADE_BUFFERS ; OFF                                ; IGNORE_CASCADE                           ;
+------------------------+------------------------------------+------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Tue Dec 12 22:37:39 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off nco -c nco
Warning: Using design file nco.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: NCO-top
    Info: Found entity 1: NCO
Info: Elaborating entity "nco" for the top level hierarchy
Warning: Using design file loadfw.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: loadfw-Load
    Info: Found entity 1: loadfw
Info: Elaborating entity "loadfw" for hierarchy "loadfw:U_loadfw"
Warning (10492): VHDL Process Statement warning at loadfw.vhd(43): signal "FREQWORD" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file loadpw.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: loadpw-Load
    Info: Found entity 1: loadpw
Info: Elaborating entity "loadpw" for hierarchy "loadpw:U_loadpw"
Warning (10492): VHDL Process Statement warning at loadpw.vhd(41): signal "PHASEWORD" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning: Using design file phasea.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: phasea-Accum
    Info: Found entity 1: phasea
Info: Elaborating entity "phasea" for hierarchy "phasea:U_phasea"
Warning (10036): Verilog HDL or VHDL warning at phasea.vhd(41): object "c4" assigned a value but never read
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Elaborating entity "lpm_add_sub" for hierarchy "phasea:U_phasea|lpm_add_sub:lpm_add_1"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Elaborating entity "addcore" for hierarchy "phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Elaborating entity "a_csnbuffer" for hierarchy "phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:oflow_node"
Info: Elaborating entity "a_csnbuffer" for hierarchy "phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Elaborating entity "altshift" for hierarchy "phasea:U_phasea|lpm_add_sub:lpm_add_1|altshift:result_ext_latency_ffs"
Info: Elaborating entity "altshift" for hierarchy "phasea:U_phasea|lpm_add_sub:lpm_add_1|altshift:carry_ext_latency_ffs"
Info: Elaborating entity "lpm_add_sub" for hierarchy "phasea:U_phasea|lpm_add_sub:lpm_add_2"
Info: Elaborating entity "lpm_add_sub" for hierarchy "phasea:U_phasea|lpm_add_sub:lpm_add_4"
Info: Elaborating entity "addcore" for hierarchy "phasea:U_phasea|lpm_add_sub:lpm_add_4|addcore:adder"
Warning: Using design file phasemod.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: phasemod-Phmodul
    Info: Found entity 1: phasemod
Info: Elaborating entity "phasemod" for hierarchy "phasemod:U_phasemod"
Warning (10036): Verilog HDL or VHDL warning at phasemod.vhd(34): object "c" assigned a value but never read
Info: Elaborating entity "lpm_add_sub" for hierarchy "phasemod:U_phasemod|lpm_add_sub:Adder"
Warning: Using design file sinlup.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: sinlup-sinlook
    Info: Found entity 1: sinlup
Info: Elaborating entity "sinlup" for hierarchy "sinlup:U_sinlup"
Warning: Using design file romtab.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: romtab-ROM
    Info: Found entity 1: romtab
Info: Elaborating entity "romtab" for hierarchy "sinlup:U_sinlup|romtab:U_romtab"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/LPM_ROM.tdf
    Info: Found entity 1: lpm_rom
Info: Elaborating entity "LPM_ROM" for hierarchy "sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altrom.tdf
    Info: Found entity 1: altrom
Info: Elaborating entity "altrom" for hierarchy "sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom"
Info: Issued messages during elaboration of megafunction "sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom", which is child of megafunction "sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component"
Info: Instantiated megafunction "sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "7"
    Info: Parameter "LPM_WIDTHAD" = "6"
    Info: Parameter "LPM_ADDRESS_CONTROL" = "REGISTERED"
    Info: Parameter "LPM_INDATA" = "REGISTERED"
    Info: Parameter "LPM_OUTDATA" = "UNREGISTERED"
    Info: Parameter "LPM_FILE" = "G:\\test\\quartus\\NCO\\ncosin.mif"
    Info: Parameter " constraint(address)" = "5 downto 0"
    Info: Parameter " constraint(q)" = "6 downto 0"
Warning: Assertion warning: altrom does not support Stratix device family -- attempting best-case memory conversions, but power-up states will be different for Stratix devices
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|altsyncram:rom_block"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_86r.tdf
    Info: Found entity 1: altsyncram_86r
Info: Elaborating entity "altsyncram_86r" for hierarchy "sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated"
Critical Warning: Can't find Memory Initialization File or Hexadecimal (Intel-Format) File G:/test/quartus/NCO/ncosin.mif -- setting all initial values to 0
Info: Ignored 3 buffer(s)
    Info: Ignored 3 SOFT buffer(s)
Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN
    Warning: Converting TRI node "sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|otri[6]" that feeds logic to a wire
    Warning: Converting TRI node "sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|otri[5]" that feeds logic to a wire
    Warning: Converting TRI node "sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|otri[4]" that feeds logic to a wire
    Warning: Converting TRI node "sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|otri[3]" that feeds logic to a wire
    Warning: Converting TRI node "sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|otri[2]" that feeds logic to a wire
    Warning: Converting TRI node "sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|otri[1]" that feeds logic to a wire
    Warning: Converting TRI node "sinlup:U_sinlup|romtab:U_romtab|lpm_rom:LPM_ROM_component|otri[0]" that feeds logic to a wire
Info: Ignored 3 buffer(s)
    Info: Ignored 3 SOFT buffer(s)
Info: Implemented 226 device resources after synthesis - the final resource count might be different
    Info: Implemented 44 input pins
    Info: Implemented 12 output pins
    Info: Implemented 163 logic cells
    Info: Implemented 7 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 21 warnings
    Info: Processing ended: Tue Dec 12 22:37:45 2006
    Info: Elapsed time: 00:00:06