nco.tan.qmsg

使用QUARTUS 2编译的DDS的源码

{ "Info" "ITDB_FULL_TCO_RESULT" "SYSCLK MCOS phasemod:U_phasemod\|mphsreg\[6\] 8.213 ns register " "Info: tco from clock \"SYSCLK\" to destination pin \"MCOS\" through register \"phasemod:U_phasemod\|mphsreg\[6\]\" is 8.213 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK source 2.786 ns + Longest register " "Info: + Longest clock path from clock \"SYSCLK\" to source register is 2.786 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SYSCLK 1 CLK PIN_L2 122 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 122; CLK Node = 'SYSCLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.519 ns) + CELL(0.542 ns) 2.786 ns phasemod:U_phasemod\|mphsreg\[6\] 2 REG LC_X31_Y24_N6 7 " "Info: 2: + IC(1.519 ns) + CELL(0.542 ns) = 2.786 ns; Loc. = LC_X31_Y24_N6; Fanout = 7; REG Node = 'phasemod:U_phasemod\|mphsreg\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.061 ns" { SYSCLK phasemod:U_phasemod|mphsreg[6] } "NODE_NAME" } "" } } { "phasemod.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasemod.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.48 % ) " "Info: Total cell delay = 1.267 ns ( 45.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.519 ns ( 54.52 % ) " "Info: Total interconnect delay = 1.519 ns ( 54.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.786 ns" { SYSCLK phasemod:U_phasemod|mphsreg[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.786 ns" { SYSCLK SYSCLK~out0 phasemod:U_phasemod|mphsreg[6] } { 0.000ns 0.000ns 1.519ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "phasemod.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasemod.vhd" 61 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.271 ns + Longest register pin " "Info: + Longest register to pin delay is 5.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns phasemod:U_phasemod\|mphsreg\[6\] 1 REG LC_X31_Y24_N6 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X31_Y24_N6; Fanout = 7; REG Node = 'phasemod:U_phasemod\|mphsreg\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "" { phasemod:U_phasemod|mphsreg[6] } "NODE_NAME" } "" } } { "phasemod.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasemod.vhd" 61 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.133 ns) + CELL(0.183 ns) 1.316 ns phasemod:U_phasemod\|MCOS~0 2 COMB LC_X31_Y22_N0 1 " "Info: 2: + IC(1.133 ns) + CELL(0.183 ns) = 1.316 ns; Loc. = LC_X31_Y22_N0; Fanout = 1; COMB Node = 'phasemod:U_phasemod\|MCOS~0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "1.316 ns" { phasemod:U_phasemod|mphsreg[6] phasemod:U_phasemod|MCOS~0 } "NODE_NAME" } "" } } { "phasemod.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasemod.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.579 ns) + CELL(2.376 ns) 5.271 ns MCOS 3 PIN PIN_L6 0 " "Info: 3: + IC(1.579 ns) + CELL(2.376 ns) = 5.271 ns; Loc. = PIN_L6; Fanout = 0; PIN Node = 'MCOS'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "3.955 ns" { phasemod:U_phasemod|MCOS~0 MCOS } "NODE_NAME" } "" } } { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.559 ns ( 48.55 % ) " "Info: Total cell delay = 2.559 ns ( 48.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.712 ns ( 51.45 % ) " "Info: Total interconnect delay = 2.712 ns ( 51.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "5.271 ns" { phasemod:U_phasemod|mphsreg[6] phasemod:U_phasemod|MCOS~0 MCOS } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.271 ns" { phasemod:U_phasemod|mphsreg[6] phasemod:U_phasemod|MCOS~0 MCOS } { 0.000ns 1.133ns 1.579ns } { 0.000ns 0.183ns 2.376ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.786 ns" { SYSCLK phasemod:U_phasemod|mphsreg[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.786 ns" { SYSCLK SYSCLK~out0 phasemod:U_phasemod|mphsreg[6] } { 0.000ns 0.000ns 1.519ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "5.271 ns" { phasemod:U_phasemod|mphsreg[6] phasemod:U_phasemod|MCOS~0 MCOS } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.271 ns" { phasemod:U_phasemod|mphsreg[6] phasemod:U_phasemod|MCOS~0 MCOS } { 0.000ns 1.133ns 1.579ns } { 0.000ns 0.183ns 2.376ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "loadfw:U_loadfw\|pipefw2\[6\] FREQWORD\[14\] SYSCLK -2.121 ns register " "Info: th for register \"loadfw:U_loadfw\|pipefw2\[6\]\" (data pin = \"FREQWORD\[14\]\", clock pin = \"SYSCLK\") is -2.121 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK destination 2.794 ns + Longest register " "Info: + Longest clock path from clock \"SYSCLK\" to destination register is 2.794 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SYSCLK 1 CLK PIN_L2 122 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 122; CLK Node = 'SYSCLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.542 ns) 2.794 ns loadfw:U_loadfw\|pipefw2\[6\] 2 REG LC_X31_Y25_N3 3 " "Info: 2: + IC(1.527 ns) + CELL(0.542 ns) = 2.794 ns; Loc. = LC_X31_Y25_N3; Fanout = 3; REG Node = 'loadfw:U_loadfw\|pipefw2\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.069 ns" { SYSCLK loadfw:U_loadfw|pipefw2[6] } "NODE_NAME" } "" } } { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.35 % ) " "Info: Total cell delay = 1.267 ns ( 45.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.527 ns ( 54.65 % ) " "Info: Total interconnect delay = 1.527 ns ( 54.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.794 ns" { SYSCLK loadfw:U_loadfw|pipefw2[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.794 ns" { SYSCLK SYSCLK~out0 loadfw:U_loadfw|pipefw2[6] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.015 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.015 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.972 ns) 0.972 ns FREQWORD\[14\] 1 PIN PIN_A11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.972 ns) = 0.972 ns; Loc. = PIN_A11; Fanout = 1; PIN Node = 'FREQWORD\[14\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "" { FREQWORD[14] } "NODE_NAME" } "" } } { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.820 ns) + CELL(0.223 ns) 5.015 ns loadfw:U_loadfw\|pipefw2\[6\] 2 REG LC_X31_Y25_N3 3 " "Info: 2: + IC(3.820 ns) + CELL(0.223 ns) = 5.015 ns; Loc. = LC_X31_Y25_N3; Fanout = 3; REG Node = 'loadfw:U_loadfw\|pipefw2\[6\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "4.043 ns" { FREQWORD[14] loadfw:U_loadfw|pipefw2[6] } "NODE_NAME" } "" } } { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.195 ns ( 23.83 % ) " "Info: Total cell delay = 1.195 ns ( 23.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.820 ns ( 76.17 % ) " "Info: Total interconnect delay = 3.820 ns ( 76.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "5.015 ns" { FREQWORD[14] loadfw:U_loadfw|pipefw2[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.015 ns" { FREQWORD[14] FREQWORD[14]~out0 loadfw:U_loadfw|pipefw2[6] } { 0.000ns 0.000ns 3.820ns } { 0.000ns 0.972ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.794 ns" { SYSCLK loadfw:U_loadfw|pipefw2[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.794 ns" { SYSCLK SYSCLK~out0 loadfw:U_loadfw|pipefw2[6] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "5.015 ns" { FREQWORD[14] loadfw:U_loadfw|pipefw2[6] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.015 ns" { FREQWORD[14] FREQWORD[14]~out0 loadfw:U_loadfw|pipefw2[6] } { 0.000ns 0.000ns 3.820ns } { 0.000ns 0.972ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 12 22:38:04 2006 " "Info: Processing ended: Tue Dec 12 22:38:04 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}