nco.tan.qmsg

使用QUARTUS 2编译的DDS的源码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "SYSCLK " "Info: Assuming node \"SYSCLK\" is an undefined clock" {  } { { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 18 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SYSCLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "SYSCLK register phasea:U_phasea\|pipe1\[3\] register phasea:U_phasea\|pipe1\[7\] 241.95 MHz 4.133 ns Internal " "Info: Clock \"SYSCLK\" has Internal fmax of 241.95 MHz between source register \"phasea:U_phasea\|pipe1\[3\]\" and destination register \"phasea:U_phasea\|pipe1\[7\]\" (period= 4.133 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.962 ns + Longest register register " "Info: + Longest register to register delay is 3.962 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns phasea:U_phasea\|pipe1\[3\] 1 REG LC_X33_Y25_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y25_N6; Fanout = 3; REG Node = 'phasea:U_phasea\|pipe1\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "" { phasea:U_phasea|pipe1[3] } "NODE_NAME" } "" } } { "phasea.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.032 ns) + CELL(0.443 ns) 1.475 ns phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~198 2 COMB LC_X34_Y21_N3 2 " "Info: 2: + IC(1.032 ns) + CELL(0.443 ns) = 1.475 ns; Loc. = LC_X34_Y21_N3; Fanout = 2; COMB Node = 'phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~198'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "1.475 ns" { phasea:U_phasea|pipe1[3] phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~198 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.130 ns) 1.605 ns phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~193 3 COMB LC_X34_Y21_N4 3 " "Info: 3: + IC(0.000 ns) + CELL(0.130 ns) = 1.605 ns; Loc. = LC_X34_Y21_N4; Fanout = 3; COMB Node = 'phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~193'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "0.130 ns" { phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~198 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~193 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.449 ns) 2.054 ns phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~176 4 COMB LC_X34_Y21_N7 2 " "Info: 4: + IC(0.000 ns) + CELL(0.449 ns) = 2.054 ns; Loc. = LC_X34_Y21_N7; Fanout = 2; COMB Node = 'phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|a_csnbuffer:result_node\|cs_buffer\[0\]~176'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "0.449 ns" { phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~193 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~176 } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 25 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(0.075 ns) 3.031 ns phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|unreg_res_node\[7\]~32 5 COMB LC_X36_Y21_N8 1 " "Info: 5: + IC(0.902 ns) + CELL(0.075 ns) = 3.031 ns; Loc. = LC_X36_Y21_N8; Fanout = 1; COMB Node = 'phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|unreg_res_node\[7\]~32'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "0.977 ns" { phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~176 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~32 } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.314 ns) + CELL(0.075 ns) 3.420 ns phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|unreg_res_node\[7\]~31 6 COMB LC_X36_Y21_N6 1 " "Info: 6: + IC(0.314 ns) + CELL(0.075 ns) = 3.420 ns; Loc. = LC_X36_Y21_N6; Fanout = 1; COMB Node = 'phasea:U_phasea\|lpm_add_sub:lpm_add_1\|addcore:adder\|unreg_res_node\[7\]~31'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "0.389 ns" { phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~32 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~31 } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.319 ns) + CELL(0.223 ns) 3.962 ns phasea:U_phasea\|pipe1\[7\] 7 REG LC_X36_Y21_N5 2 " "Info: 7: + IC(0.319 ns) + CELL(0.223 ns) = 3.962 ns; Loc. = LC_X36_Y21_N5; Fanout = 2; REG Node = 'phasea:U_phasea\|pipe1\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "0.542 ns" { phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~31 phasea:U_phasea|pipe1[7] } "NODE_NAME" } "" } } { "phasea.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.395 ns ( 35.21 % ) " "Info: Total cell delay = 1.395 ns ( 35.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.567 ns ( 64.79 % ) " "Info: Total interconnect delay = 2.567 ns ( 64.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "3.962 ns" { phasea:U_phasea|pipe1[3] phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~198 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~193 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~176 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~32 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~31 phasea:U_phasea|pipe1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.962 ns" { phasea:U_phasea|pipe1[3] phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~198 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~193 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~176 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~32 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~31 phasea:U_phasea|pipe1[7] } { 0.000ns 1.032ns 0.000ns 0.000ns 0.902ns 0.314ns 0.319ns } { 0.000ns 0.443ns 0.130ns 0.449ns 0.075ns 0.075ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.005 ns - Smallest " "Info: - Smallest clock skew is -0.005 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK destination 2.789 ns + Shortest register " "Info: + Shortest clock path from clock \"SYSCLK\" to destination register is 2.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SYSCLK 1 CLK PIN_L2 122 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 122; CLK Node = 'SYSCLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.522 ns) + CELL(0.542 ns) 2.789 ns phasea:U_phasea\|pipe1\[7\] 2 REG LC_X36_Y21_N5 2 " "Info: 2: + IC(1.522 ns) + CELL(0.542 ns) = 2.789 ns; Loc. = LC_X36_Y21_N5; Fanout = 2; REG Node = 'phasea:U_phasea\|pipe1\[7\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.064 ns" { SYSCLK phasea:U_phasea|pipe1[7] } "NODE_NAME" } "" } } { "phasea.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.43 % ) " "Info: Total cell delay = 1.267 ns ( 45.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.522 ns ( 54.57 % ) " "Info: Total interconnect delay = 1.522 ns ( 54.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.789 ns" { SYSCLK phasea:U_phasea|pipe1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.789 ns" { SYSCLK SYSCLK~out0 phasea:U_phasea|pipe1[7] } { 0.000ns 0.000ns 1.522ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK source 2.794 ns - Longest register " "Info: - Longest clock path from clock \"SYSCLK\" to source register is 2.794 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SYSCLK 1 CLK PIN_L2 122 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 122; CLK Node = 'SYSCLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.527 ns) + CELL(0.542 ns) 2.794 ns phasea:U_phasea\|pipe1\[3\] 2 REG LC_X33_Y25_N6 3 " "Info: 2: + IC(1.527 ns) + CELL(0.542 ns) = 2.794 ns; Loc. = LC_X33_Y25_N6; Fanout = 3; REG Node = 'phasea:U_phasea\|pipe1\[3\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.069 ns" { SYSCLK phasea:U_phasea|pipe1[3] } "NODE_NAME" } "" } } { "phasea.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 79 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.35 % ) " "Info: Total cell delay = 1.267 ns ( 45.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.527 ns ( 54.65 % ) " "Info: Total interconnect delay = 1.527 ns ( 54.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.794 ns" { SYSCLK phasea:U_phasea|pipe1[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.794 ns" { SYSCLK SYSCLK~out0 phasea:U_phasea|pipe1[3] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.789 ns" { SYSCLK phasea:U_phasea|pipe1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.789 ns" { SYSCLK SYSCLK~out0 phasea:U_phasea|pipe1[7] } { 0.000ns 0.000ns 1.522ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.794 ns" { SYSCLK phasea:U_phasea|pipe1[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.794 ns" { SYSCLK SYSCLK~out0 phasea:U_phasea|pipe1[3] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "phasea.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 79 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "phasea.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/phasea.vhd" 79 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "3.962 ns" { phasea:U_phasea|pipe1[3] phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~198 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~193 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~176 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~32 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~31 phasea:U_phasea|pipe1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.962 ns" { phasea:U_phasea|pipe1[3] phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~198 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~193 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~176 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~32 phasea:U_phasea|lpm_add_sub:lpm_add_1|addcore:adder|unreg_res_node[7]~31 phasea:U_phasea|pipe1[7] } { 0.000ns 1.032ns 0.000ns 0.000ns 0.902ns 0.314ns 0.319ns } { 0.000ns 0.443ns 0.130ns 0.449ns 0.075ns 0.075ns 0.223ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.789 ns" { SYSCLK phasea:U_phasea|pipe1[7] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.789 ns" { SYSCLK SYSCLK~out0 phasea:U_phasea|pipe1[7] } { 0.000ns 0.000ns 1.522ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.794 ns" { SYSCLK phasea:U_phasea|pipe1[3] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.794 ns" { SYSCLK SYSCLK~out0 phasea:U_phasea|pipe1[3] } { 0.000ns 0.000ns 1.527ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "loadfw:U_loadfw\|pipefw2\[2\] RESETN SYSCLK 5.129 ns register " "Info: tsu for register \"loadfw:U_loadfw\|pipefw2\[2\]\" (data pin = \"RESETN\", clock pin = \"SYSCLK\") is 5.129 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.908 ns + Longest pin register " "Info: + Longest pin to register delay is 7.908 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns RESETN 1 PIN PIN_C9 121 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_C9; Fanout = 121; PIN Node = 'RESETN'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "" { RESETN } "NODE_NAME" } "" } } { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.657 ns) + CELL(0.280 ns) 6.024 ns loadfw:U_loadfw\|pipefw2\[1\]~139 2 COMB LC_X31_Y25_N7 8 " "Info: 2: + IC(4.657 ns) + CELL(0.280 ns) = 6.024 ns; Loc. = LC_X31_Y25_N7; Fanout = 8; COMB Node = 'loadfw:U_loadfw\|pipefw2\[1\]~139'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "4.937 ns" { RESETN loadfw:U_loadfw|pipefw2[1]~139 } "NODE_NAME" } "" } } { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.179 ns) + CELL(0.705 ns) 7.908 ns loadfw:U_loadfw\|pipefw2\[2\] 3 REG LC_X33_Y21_N5 3 " "Info: 3: + IC(1.179 ns) + CELL(0.705 ns) = 7.908 ns; Loc. = LC_X33_Y21_N5; Fanout = 3; REG Node = 'loadfw:U_loadfw\|pipefw2\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "1.884 ns" { loadfw:U_loadfw|pipefw2[1]~139 loadfw:U_loadfw|pipefw2[2] } "NODE_NAME" } "" } } { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.072 ns ( 26.20 % ) " "Info: Total cell delay = 2.072 ns ( 26.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.836 ns ( 73.80 % ) " "Info: Total interconnect delay = 5.836 ns ( 73.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "7.908 ns" { RESETN loadfw:U_loadfw|pipefw2[1]~139 loadfw:U_loadfw|pipefw2[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.908 ns" { RESETN RESETN~out0 loadfw:U_loadfw|pipefw2[1]~139 loadfw:U_loadfw|pipefw2[2] } { 0.000ns 0.000ns 4.657ns 1.179ns } { 0.000ns 1.087ns 0.280ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "SYSCLK destination 2.789 ns - Shortest register " "Info: - Shortest clock path from clock \"SYSCLK\" to destination register is 2.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns SYSCLK 1 CLK PIN_L2 122 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 122; CLK Node = 'SYSCLK'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "" { SYSCLK } "NODE_NAME" } "" } } { "nco.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/nco.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.522 ns) + CELL(0.542 ns) 2.789 ns loadfw:U_loadfw\|pipefw2\[2\] 2 REG LC_X33_Y21_N5 3 " "Info: 2: + IC(1.522 ns) + CELL(0.542 ns) = 2.789 ns; Loc. = LC_X33_Y21_N5; Fanout = 3; REG Node = 'loadfw:U_loadfw\|pipefw2\[2\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.064 ns" { SYSCLK loadfw:U_loadfw|pipefw2[2] } "NODE_NAME" } "" } } { "loadfw.vhd" "" { Text "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/loadfw.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 45.43 % ) " "Info: Total cell delay = 1.267 ns ( 45.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.522 ns ( 54.57 % ) " "Info: Total interconnect delay = 1.522 ns ( 54.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.789 ns" { SYSCLK loadfw:U_loadfw|pipefw2[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.789 ns" { SYSCLK SYSCLK~out0 loadfw:U_loadfw|pipefw2[2] } { 0.000ns 0.000ns 1.522ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "7.908 ns" { RESETN loadfw:U_loadfw|pipefw2[1]~139 loadfw:U_loadfw|pipefw2[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.908 ns" { RESETN RESETN~out0 loadfw:U_loadfw|pipefw2[1]~139 loadfw:U_loadfw|pipefw2[2] } { 0.000ns 0.000ns 4.657ns 1.179ns } { 0.000ns 1.087ns 0.280ns 0.705ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "nco" "UNKNOWN" "V1" "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/db/nco.quartus_db" { Floorplan "C:/Documents and Settings/wu/My Documents/DDS/ddsVHDL/dds/dds/" "" "2.789 ns" { SYSCLK loadfw:U_loadfw|pipefw2[2] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.789 ns" { SYSCLK SYSCLK~out0 loadfw:U_loadfw|pipefw2[2] } { 0.000ns 0.000ns 1.522ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}