nco.hier_info

使用QUARTUS 2编译的DDS的源码

cout[7] <= cout[7]~0.DB_MAX_OUTPUT_PORT_TYPE


|nco|phasemod:U_phasemod|lpm_add_sub:Adder|addcore:adder|a_csnbuffer:result_node
sin[0] => cs_buffer[0].SUM_IN
sin[1] => cs_buffer[1].SUM_IN
sin[2] => cs_buffer[2].SUM_IN
sin[3] => cs_buffer[3].SUM_IN
sin[4] => cs_buffer[4].SUM_IN
sin[5] => cs_buffer[5].SUM_IN
sin[6] => cs_buffer[6].SUM_IN
sin[7] => cs_buffer[7].SUM_IN
cin[0] => cs_buffer[0].CIN
cin[1] => cs_buffer[1].CIN
cin[2] => cs_buffer[2].CIN
cin[3] => cs_buffer[3].CIN
cin[4] => cs_buffer[4].CIN
cin[5] => cs_buffer[5].CIN
cin[6] => cs_buffer[6].CIN
cin[7] => cs_buffer[7].CIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= cs_buffer[0].DB_MAX_OUTPUT_PORT_TYPE
sout[1] <= cs_buffer[1].DB_MAX_OUTPUT_PORT_TYPE
sout[2] <= cs_buffer[2].DB_MAX_OUTPUT_PORT_TYPE
sout[3] <= cs_buffer[3].DB_MAX_OUTPUT_PORT_TYPE
sout[4] <= cs_buffer[4].DB_MAX_OUTPUT_PORT_TYPE
sout[5] <= cs_buffer[5].DB_MAX_OUTPUT_PORT_TYPE
sout[6] <= cs_buffer[6].DB_MAX_OUTPUT_PORT_TYPE
sout[7] <= cs_buffer[7].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cs_buffer[0].DB_MAX_OUTPUT_PORT_TYPE
cout[1] <= cs_buffer[1].DB_MAX_OUTPUT_PORT_TYPE
cout[2] <= cs_buffer[2].DB_MAX_OUTPUT_PORT_TYPE
cout[3] <= cs_buffer[3].DB_MAX_OUTPUT_PORT_TYPE
cout[4] <= cs_buffer[4].DB_MAX_OUTPUT_PORT_TYPE
cout[5] <= cs_buffer[5].DB_MAX_OUTPUT_PORT_TYPE
cout[6] <= cs_buffer[6].DB_MAX_OUTPUT_PORT_TYPE
cout[7] <= cs_buffer[7].DB_MAX_OUTPUT_PORT_TYPE


|nco|phasemod:U_phasemod|lpm_add_sub:Adder|addcore:adder|a_csnbuffer:cout_node
sin[0] => sout_node[0].DATAIN
sin[1] => sout_node[1].DATAIN
sin[2] => sout_node[2].DATAIN
sin[3] => sout_node[3].DATAIN
sin[4] => sout_node[4].DATAIN
sin[5] => sout_node[5].DATAIN
sin[6] => sout_node[6].DATAIN
sin[7] => sout_node[7].DATAIN
cin[0] => cout[0]~7.IN0
cin[1] => cout[1]~6.IN0
cin[2] => cout[2]~5.IN0
cin[3] => cout[3]~4.IN0
cin[4] => cout[4]~3.IN0
cin[5] => cout[5]~2.IN0
cin[6] => cout[6]~1.IN0
cin[7] => cout[7]~0.IN0
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
sout[1] <= sout_node[1].DB_MAX_OUTPUT_PORT_TYPE
sout[2] <= sout_node[2].DB_MAX_OUTPUT_PORT_TYPE
sout[3] <= sout_node[3].DB_MAX_OUTPUT_PORT_TYPE
sout[4] <= sout_node[4].DB_MAX_OUTPUT_PORT_TYPE
sout[5] <= sout_node[5].DB_MAX_OUTPUT_PORT_TYPE
sout[6] <= sout_node[6].DB_MAX_OUTPUT_PORT_TYPE
sout[7] <= sout_node[7].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~7.DB_MAX_OUTPUT_PORT_TYPE
cout[1] <= cout[1]~6.DB_MAX_OUTPUT_PORT_TYPE
cout[2] <= cout[2]~5.DB_MAX_OUTPUT_PORT_TYPE
cout[3] <= cout[3]~4.DB_MAX_OUTPUT_PORT_TYPE
cout[4] <= cout[4]~3.DB_MAX_OUTPUT_PORT_TYPE
cout[5] <= cout[5]~2.DB_MAX_OUTPUT_PORT_TYPE
cout[6] <= cout[6]~1.DB_MAX_OUTPUT_PORT_TYPE
cout[7] <= cout[7]~0.DB_MAX_OUTPUT_PORT_TYPE


|nco|phasemod:U_phasemod|lpm_add_sub:Adder|altshift:result_ext_latency_ffs
data[0] => result[0].DATAIN
data[1] => result[1].DATAIN
data[2] => result[2].DATAIN
data[3] => result[3].DATAIN
data[4] => result[4].DATAIN
data[5] => result[5].DATAIN
data[6] => result[6].DATAIN
data[7] => result[7].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE


|nco|phasemod:U_phasemod|lpm_add_sub:Adder|altshift:carry_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|nco|phasemod:U_phasemod|lpm_add_sub:Adder|altshift:oflow_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|nco|sinlup:U_sinlup
SYSCLK => modphase_msb2_ff.CLK
SYSCLK => phaseadd[5].CLK
SYSCLK => phaseadd[4].CLK
SYSCLK => phaseadd[3].CLK
SYSCLK => phaseadd[2].CLK
SYSCLK => phaseadd[1].CLK
SYSCLK => phaseadd[0].CLK
SYSCLK => qwavesin_ff[6].CLK
SYSCLK => qwavesin_ff[5].CLK
SYSCLK => qwavesin_ff[4].CLK
SYSCLK => qwavesin_ff[3].CLK
SYSCLK => qwavesin_ff[2].CLK
SYSCLK => qwavesin_ff[1].CLK
SYSCLK => qwavesin_ff[0].CLK
SYSCLK => NCOOUT[7]~reg0.CLK
SYSCLK => NCOOUT[6]~reg0.CLK
SYSCLK => NCOOUT[5]~reg0.CLK
SYSCLK => NCOOUT[4]~reg0.CLK
SYSCLK => NCOOUT[3]~reg0.CLK
SYSCLK => NCOOUT[2]~reg0.CLK
SYSCLK => NCOOUT[1]~reg0.CLK
SYSCLK => NCOOUT[0]~reg0.CLK
SYSCLK => modphase_msb3_ff.CLK
SYSCLK => romtab:U_romtab.SYSCLK
SYSCLK => modphase_msb1_ff.CLK
RESETN => modphase_msb1_ff~0.OUTPUTSELECT
RESETN => modphase_msb2_ff~0.OUTPUTSELECT
RESETN => phaseadd~6.OUTPUTSELECT
RESETN => phaseadd~7.OUTPUTSELECT
RESETN => phaseadd~8.OUTPUTSELECT
RESETN => phaseadd~9.OUTPUTSELECT
RESETN => phaseadd~10.OUTPUTSELECT
RESETN => phaseadd~11.OUTPUTSELECT
RESETN => qwavesin_ff~0.OUTPUTSELECT
RESETN => qwavesin_ff~1.OUTPUTSELECT
RESETN => qwavesin_ff~2.OUTPUTSELECT
RESETN => qwavesin_ff~3.OUTPUTSELECT
RESETN => qwavesin_ff~4.OUTPUTSELECT
RESETN => qwavesin_ff~5.OUTPUTSELECT
RESETN => qwavesin_ff~6.OUTPUTSELECT
RESETN => NCOOUT~7.OUTPUTSELECT
RESETN => NCOOUT~8.OUTPUTSELECT
RESETN => NCOOUT~9.OUTPUTSELECT
RESETN => NCOOUT~10.OUTPUTSELECT
RESETN => NCOOUT~11.OUTPUTSELECT
RESETN => NCOOUT~12.OUTPUTSELECT
RESETN => NCOOUT~13.OUTPUTSELECT
RESETN => NCOOUT~14.OUTPUTSELECT
RESETN => modphase_msb3_ff.ENA
MODPHASE[0] => phaseadd~5.DATAA
MODPHASE[0] => phaseadd~5.DATAB
MODPHASE[1] => phaseadd~4.DATAA
MODPHASE[1] => phaseadd~4.DATAB
MODPHASE[2] => phaseadd~3.DATAA
MODPHASE[2] => phaseadd~3.DATAB
MODPHASE[3] => phaseadd~2.DATAA
MODPHASE[3] => phaseadd~2.DATAB
MODPHASE[4] => phaseadd~1.DATAA
MODPHASE[4] => phaseadd~1.DATAB
MODPHASE[5] => phaseadd~0.DATAA
MODPHASE[5] => phaseadd~0.DATAB
MODPHASE[6] => phaseadd~0.OUTPUTSELECT
MODPHASE[6] => phaseadd~1.OUTPUTSELECT
MODPHASE[6] => phaseadd~2.OUTPUTSELECT
MODPHASE[6] => phaseadd~3.OUTPUTSELECT
MODPHASE[6] => phaseadd~4.OUTPUTSELECT
MODPHASE[6] => phaseadd~5.OUTPUTSELECT
MODPHASE[7] => modphase_msb1_ff~0.DATAA
NCOOUT[0] <= NCOOUT[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
NCOOUT[1] <= NCOOUT[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
NCOOUT[2] <= NCOOUT[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
NCOOUT[3] <= NCOOUT[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
NCOOUT[4] <= NCOOUT[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
NCOOUT[5] <= NCOOUT[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
NCOOUT[6] <= NCOOUT[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
NCOOUT[7] <= NCOOUT[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|nco|sinlup:U_sinlup|romtab:U_romtab
SYSCLK => LPM_ROM:LPM_ROM_component.inclock
PHASEADD[0] => LPM_ROM:LPM_ROM_component.address[0]
PHASEADD[1] => LPM_ROM:LPM_ROM_component.address[1]
PHASEADD[2] => LPM_ROM:LPM_ROM_component.address[2]
PHASEADD[3] => LPM_ROM:LPM_ROM_component.address[3]
PHASEADD[4] => LPM_ROM:LPM_ROM_component.address[4]
PHASEADD[5] => LPM_ROM:LPM_ROM_component.address[5]
QWAVESIN[0] <= LPM_ROM:LPM_ROM_component.q[0]
QWAVESIN[1] <= LPM_ROM:LPM_ROM_component.q[1]
QWAVESIN[2] <= LPM_ROM:LPM_ROM_component.q[2]
QWAVESIN[3] <= LPM_ROM:LPM_ROM_component.q[3]
QWAVESIN[4] <= LPM_ROM:LPM_ROM_component.q[4]
QWAVESIN[5] <= LPM_ROM:LPM_ROM_component.q[5]
QWAVESIN[6] <= LPM_ROM:LPM_ROM_component.q[6]


|nco|sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
inclock => altrom:srom.clocki
outclock => ~NO_FANOUT~
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE


|nco|sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom
address[0] => altsyncram:rom_block.address_a[0]
address[1] => altsyncram:rom_block.address_a[1]
address[2] => altsyncram:rom_block.address_a[2]
address[3] => altsyncram:rom_block.address_a[3]
address[4] => altsyncram:rom_block.address_a[4]
address[5] => altsyncram:rom_block.address_a[5]
clocki => altsyncram:rom_block.clock0
clocko => ~NO_FANOUT~
q[0] <= altsyncram:rom_block.q_a[0]
q[1] <= altsyncram:rom_block.q_a[1]
q[2] <= altsyncram:rom_block.q_a[2]
q[3] <= altsyncram:rom_block.q_a[3]
q[4] <= altsyncram:rom_block.q_a[4]
q[5] <= altsyncram:rom_block.q_a[5]
q[6] <= altsyncram:rom_block.q_a[6]


|nco|sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|altsyncram:rom_block
wren_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_86r:auto_generated.address_a[0]
address_a[1] => altsyncram_86r:auto_generated.address_a[1]
address_a[2] => altsyncram_86r:auto_generated.address_a[2]
address_a[3] => altsyncram_86r:auto_generated.address_a[3]
address_a[4] => altsyncram_86r:auto_generated.address_a[4]
address_a[5] => altsyncram_86r:auto_generated.address_a[5]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_86r:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_86r:auto_generated.q_a[0]
q_a[1] <= altsyncram_86r:auto_generated.q_a[1]
q_a[2] <= altsyncram_86r:auto_generated.q_a[2]
q_a[3] <= altsyncram_86r:auto_generated.q_a[3]
q_a[4] <= altsyncram_86r:auto_generated.q_a[4]
q_a[5] <= altsyncram_86r:auto_generated.q_a[5]
q_a[6] <= altsyncram_86r:auto_generated.q_a[6]
q_b[0] <= <GND>


|nco|sinlup:U_sinlup|romtab:U_romtab|LPM_ROM:LPM_ROM_component|altrom:srom|altsyncram:rom_block|altsyncram_86r:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT